2022
DOI: 10.1109/tcsii.2022.3143504
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Offset-Compensation High-Performance Sense Amplifier for Low-Voltage DRAM Based on Current Mirror and Switching Point

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Cited by 5 publications
(1 citation statement)
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“…The precharge circuit is comprised of three NMOS transistors controlled by the PRE signal. At each operation cycle, the bitlines are charged to VDD/2 before accessing the DRAM cells [19]. The bitline nodes at the IO interface can transfer the amplified voltage to the IO bus or be driven by the write drivers with the help of IO transistors.…”
Section: Introductionmentioning
confidence: 99%
“…The precharge circuit is comprised of three NMOS transistors controlled by the PRE signal. At each operation cycle, the bitlines are charged to VDD/2 before accessing the DRAM cells [19]. The bitline nodes at the IO interface can transfer the amplified voltage to the IO bus or be driven by the write drivers with the help of IO transistors.…”
Section: Introductionmentioning
confidence: 99%