OFF-State leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current

Threshold voltage shift of submicron p-channel MOSFET due to Si surface damage from plasma etching process

“…Although the threshold voltage of the dry etched sample is only 70 mV higher than that for the wet etched sample, the off-state leakage current for the dry etched structure increases dramatically. It is known that the off-state leakage current for MOS transistors is mainly determined by the sub-threshold off current, GIDL, and junction leakage currents [16]. From these data, it is evidently clear that plasma processing leads to the degradation of the transistor.…”

Novel tri-state inverter based on junction band-to-band tunneling-enhanced silicon nanoscale CMOS technology

“…Figure 3 shows that the difference of 10 ff in n/pMOS can control the voltage level of intermediate state. In general, 10ff of MOSFET is determined by gate leakage and pn junction between SID and substrate [13,14]. The 10ff difference between n/pMOS is occurred by junction of source-substrate-drain, npn of nMOS and pnp of pMOS.…”

Analysis of Self-Heating in Poly-Si Thin-Film Transistors and Circuits by a Self-Consistent Electro-Thermal Simulation Approach

“…Assuming that the CMOS IC can be considered as composed of and "equivalent" number of two-input NAND, and two-input NOR gates, with effective transistor size [8], the average standby leakage power with and without considering the electro-thermal coupling is calculated at different initial ambient temperature, as shown in Fig.11. The coupling between the temperature and I OFF introduce much higher power consumption, which may in turn result in a high local temperature.…”