Novel tri-state inverter based on junction band-to-band tunneling-enhanced silicon nanoscale CMOS technology

Abstract

We propose a novel tri-state inverter based on junction band-to-band tunneling (BTBT)-enhanced nanoscale CMOS structure. By suppressing the gate-induced drain leakage (GIDL) current, an additional stable state, "112", can be generated with intermediate level from voltage dividing in series resistance of off-state n/pMOS. The high-speed performance of our proposed tri-state inverter has been estimated with the junction BTBT-enhanced 45 nm Si CMOS technology.