1995
DOI: 10.1016/0304-3886(95)00031-5
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Off-chip protection: Shunting of ESD current by metal fingers on integrated circuits and printed circuit boards

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Cited by 6 publications
(4 citation statements)
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“…3(b). At a given frequency (ω), this series configuration can be transformed to the parallel configuration [6]. The quality factor (Q) is defined as Equation 1a.…”
Section: (3) Signal Switching Time Increases Test Time Costs and Relamentioning
confidence: 99%
“…3(b). At a given frequency (ω), this series configuration can be transformed to the parallel configuration [6]. The quality factor (Q) is defined as Equation 1a.…”
Section: (3) Signal Switching Time Increases Test Time Costs and Relamentioning
confidence: 99%
“…At a given frequency ( ω ), this series configuration can be transformed to the parallel configuration (see Fig. 5 b ) [16]. The quality factor ( Q ) is defined as (1a).…”
Section: Numerical Validationmentioning
confidence: 99%
“…Numerical validation a Equivalent circuit model of the evaluated PCB for numerical validation. The equivalent circuit model includes: (i) the circuit model of the LNA based on the ADS2009 simulator in chipset under test, (ii) a parallel RC network to represent the ESD protection diode, (iii) a microstrip transmission line and (iv) a resistance of R_pogo pin series with a π‐network to present the pogo pin b Simplified RF modelling of ESD protection devices and its parallel configuration [16]…”
Section: Numerical Validationmentioning
confidence: 99%
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