OCCN: a NoC modeling framework for design exploration

Coppola, Marcello; Curaba, Stephane; Grammatikakis, Miltos D.; Locatelli, Riccardo; Maruccia, Giuseppe; Papariello, Francesco

doi:10.1016/j.sysarc.2003.07.002

Cited by 23 publications

(6 citation statements)

References 31 publications

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“…A summary of available communication primitives at different levels of abstractions can be found in [25,71]. Based on analysis discussed in [35], there are five abstraction levels, as they are depicted in Fig. 2.16.…”

Section: Different Abstraction Levels For Noc Modelingmentioning

confidence: 99%

NoC Modeling and Topology Exploration

Tatas

Siozios

Soudris

et al. 2013

Designing 2D and 3D Network-on-Chip Architectures

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This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints. IntroductionWith the advent of chip multi-processors (CMP) and multi-core systems-on-chip (SoC), the network-on-chip (NoC) paradigm has been proposed as a viable solution to the problem of connecting the continuously increasing number of processing cores that are integrated on a single die. The communication problem is expected to become far more important with the demand for higher processing power posed by the majority of application domains and the technology scaling.Even though the NoC-based communication scheme introduces architectural scalability and performance enhancement, as already discussed in Chap. 1, however, careful design is absolutely required in order to achieve these gains. In this chapter, we discuss a number of architectural issues related to widely accepted NoC topologies. Additionally, the available academic and commercial solutions for topology modeling and synthesis are presented, whereas the main features/limitations for each of them are highlighted. In order to quantify the efficiency for each architectural selection, appropriate benchmarks are also required. For this purpose, throughout the second chapter we also introduce a number of typical traffic models employed for the scope of evaluating NoC architectures. Since the design, as well as the quantification of these NoC parameters are rather complex tasks, which cannot be easily performed without the usage of dedicated software tools, a number of frameworks are also introduced.K. Tatas et al., Designing 2D and 3D Network-on-Chip Architectures,

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Section: Different Abstraction Levels For Noc Modelingmentioning

confidence: 99%

NoC Modeling and Topology Exploration

Tatas

Siozios

Soudris

et al. 2013

Designing 2D and 3D Network-on-Chip Architectures

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“…In particular, there are two fields which are contributing to the research on OCAs. The first is the research community where new OCA design alternatives are proposed, modeled, implemented and evaluated [Taylor et al 2002;Millberg et al 2004;Sonics Inc. 2003;Adriahantenaina et al 2003;Coppola 2003]. The second field is the EDA community where new design methodology and CAD tools are proposed to expedite the design process for the novel design paradigms.…”

Section: Related Workmentioning

confidence: 99%

A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs

Zhu

Malik

2007

ACM Trans. Des. Autom. Electron. Syst.

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In multiprocessor-based SoCs, optimizing the communication architecture is often as important, if not more important, than optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of architectures of processing elements, the same is not true for the communication architectures. This article presents an application-driven retargetable prototyping platform that fills this gap. This environment aims to facilitate the design exploration of the communication subsystem through application-level execution-driven simulations and quantitative analysis. Based on an analysis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or variants of existing ones with relatively little incremental effort. We demonstrate this through three case studies including two commercial on-chip bus systems and an on-chip packet switching network. Here we show that, through careful analysis and construction, it is possible for the modeling environment to support the common features of these architectures as part of the library and permit instantiation of the individual architectures as variants of the library design. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in the early stages of design. In addition to improving design quality, this methodology also results in significantly shortening design-time.

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“…[7] discusses the development of a SystemC-based cycle accurate simulator for a cluster of ARM processors. OCCN [2] is an open-source research framework for OCA modeling based on SystemC. Even though both of them and similar work in [15] target the design exploration of OCAs, currently they only examine the on-chip bus and its variants as OCA candidates.…”

Section: Related Workmentioning

confidence: 99%

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

Zhu

Qin

Malik

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

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In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation archi-tectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This paper presents a mod-eling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the Operation State Machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchi-tecture level concurrencies of OCAs as well, our OSM-based mod-eling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA: a 4x4 mesh network of 16 PEs, and a cluster of 4 PEs connected by a bus. We show that by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design. In addition to improving design quality, this methodology also results in significantly shortened design-time.

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OCCN: a NoC modeling framework for design exploration

Abstract: The On-Chip Communication Network (OCCN)

Cited by 23 publications

References 31 publications

NoC Modeling and Topology Exploration

NoC Modeling and Topology Exploration

A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

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