Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction

Lee, Lung-Jen

doi:10.1007/s10836-013-5404-x

Cited by 3 publications

(1 citation statement)

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“…Additionally, layout-aware techniques were proposed to increase the accuracy of the switching activity estimation targeting critical areas [18,19]. The works in [2,11] use information about control signals of clock gating cells to disable certain areas during test, whereas the approach in [20] groups and disables scan chains.…”

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confidence: 99%

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Eggersglüβ

2014

J Electron Test

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Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic Xfilling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.

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confidence: 99%