Null convention logic (NCL) based asynchronous design — fundamentals and recent advances

Tran, Linh Duc; Matthews, Glenn I.; Beckett, Paul; Stojcevski, Alex

doi:10.1109/sigtelcom.2017.7849815

Cited by 19 publications

(10 citation statements)

References 26 publications

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“…43,44 Null convention logic typically alleviates the clock trees synthesis and power issues at the cost of area and physical layout complexity. 43,44 Null convention logic typically alleviates the clock trees synthesis and power issues at the cost of area and physical layout complexity.…”

Section: Run-time/design-time Adjustable Threshold Logicmentioning

confidence: 99%

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A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Ghaffarishad

Mohammadzadeh

Ghaznavi‐Ghoushchi

2018

Circuit Theory & Apps

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The continued downscaling of CMOS technology has resulted in very high performance devices, but power dissipation is a limiting factor on this way. Power and performance of a device are dependent on process, temperature, and workload variation that makes it impossible to find a single power optimal design. As a result, adaptive power and performance adjustment techniques emerged as attractive methods to improve the effective power efficiency of a device in modern design approaches. Focusing on this issue, in this paper, a novel logic family is proposed that enables tuning the transistor's effective threshold voltage after fabrication for higher speed or lower power. This method along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the workload requirement. The externally static topology of the proposed logic makes it possible to replace static circuits without requiring significant changes in the system. Experimental results obtained using 90-nm CMOS standard technology show that the proposed logic improves the average powerdelay product by about 40% for the attempted benchmarks. KEYWORDS adaptive voltage scaling (AVS), digital logic design, power-performance tunable logic, pseudodynamic logic | INTRODUCTIONIn the past few decades, digital circuit performance improved rapidly; mostly enabled by aggressive improvement of transistor performance. The exponential decrease in transistor feature sizes accompanied by exponential increase in transistor-switching speed has led to incredible computing power in today's integrated circuit. However, these devices have serious limitations on power dissipation. Obtaining energy efficiency and low peak power while maintaining computational performance is one of the primary goals in contemporary processor design.Transistor variability in very-large-scale integrated circuit. Increases with the very-large-scale integration process technology scaling trend, as smaller transistors have higher circuit parameter uncertainties. On the other hand, the off-leakage current of sub-100 nm processes is considerable. 1 In other words, in the sub-100 nm processes, the off-leakage power is a significant portion of the total power consumed by a circuit. For example, at the 90-nm technology node, leakage power may make up 42% of total power. 2 Beyond the circuit topology, the major factor in control and reduction of leakage power and current is the MOS transistors threshold voltage altering. Threshold voltage is subject of 2 different kinds of controllability: design-time and run-

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Section: Run-time/design-time Adjustable Threshold Logicmentioning

confidence: 99%

“…In recent submicron evaluations, the power and timing are considered with different approaches including asynchronous trends like null convention logic. 43,44 Null convention logic typically alleviates the clock trees synthesis and power issues at the cost of area and physical layout complexity.…”

Section: Run-time/design-time Adjustable Threshold Logicmentioning

confidence: 99%

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Ghaffarishad

Mohammadzadeh

Ghaznavi‐Ghoushchi

2018

Circuit Theory & Apps

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“…For illustration, the TH23 NCL gate shown in Figure. 3 has been implemented in static CMOS technology. In [17][18][19][20] three basic gates architectures that implement NCL threshold gates have been proposed for applications that involve standard-cell VLSI or FPGA platforms. In order to operate correctly, these architectures must obey the fundamental mode (FM), therefore they are not QDI.…”

Section: This Paper Is An Extension Of Work Originally Presented In 2mentioning

confidence: 99%

“…The implemented THmn NCL gates in the Huffman machine architecture [17][18][19][20] (see Figure. 5) can be synthesized by the Huffman method [3].…”

Section: Synthesizing Huffman Machines As Ncl Gatesmentioning

confidence: 99%

Synthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates

Oliveira¹,

Verducci²,

Torres³

et al. 2018

Adv. sci. technol. eng. syst. j.

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Currently, synchronous digital circuits (SDC) may require certain design conditions, such as power consumption, robustness, performance, etc. These design conditions are more difficult to satisfy when SDC are implemented in VLSI (Very Large Scale Integration) technology and in the deep-sub-micron MOS (DSM-MOS) technology. The asynchronous design style has properties that serve as an alternative to design DSM-MOS technology circuits and it can satisfy these design conditions. Quasi Delay-Insensitive (QDI) circuits is a class of asynchronous circuits, they have properties where the DSM-MOS technology design is applied, because they are robust to noise, temperature and voltage variations, as well as low electromagnetic emissions, and they are tolerant to certain faults. An interesting style of QDI combinational circuits are NCL (NULL Convention Logic) circuits, because they accept conventional Boolean functions and it can achieve a better optimization. This paper presents an approach and an architecture based in basic gates for the synthesis of NCL gates, therefore its implementation uses only standard libraries and Field Programmable Gate Array (FPGA). The proposed QDI combinational circuits are implemented in the approach that uses only NCL gates.

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“…Among asynchronous QDI design approaches, NCL is the most robust methodology with advantages in low‐power consumption, optimisation potential and integration ability [2, 17]. NCL utilises return‐to‐zero ( RTZ ) delay‐insensitive (DI) codes, typically a dual‐rail encoding scheme to encode data values with two mutually‐exclusive wires for each binary bit (Fig.…”

Section: Introductionmentioning

confidence: 99%

Extended Boolean algebra for asynchronous quasi‐delay‐insensitive logic

Tran

Pham

Kavehei

et al. 2020

IET Circuits, Devices & Systems

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Null convention logic (NCL) based asynchronous design — fundamentals and recent advances

Cited by 19 publications

References 26 publications

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility

Synthesis of QDI Combinational Circuits using Null Convention Logic Based on Basic Gates

Extended Boolean algebra for asynchronous quasi‐delay‐insensitive logic

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