NUAT: A non-uniform access time memory controller

Shin, Wongyu; Yang, Jung‐Seok; Choi, Jungwhan; Kim, Lee-Sup

doi:10.1109/hpca.2014.6835956

Cited by 63 publications

(52 citation statements)

References 16 publications

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“…Even though some of the observations in [65] are similar to ours, the approaches to leverage them are different. AL-DRAM exploits temperature dependence in a DIMM and process variations across DIMMs.…”

Section: Related Workmentioning

confidence: 80%

“…Several works investigated the possibility of reducing DRAM latency by either exploiting DRAM latency variation [7,65] or changing the DRAM architecture [34,36,45,61,62,66]. We discuss these below.…”

Section: Related Workmentioning

confidence: 99%

“…Shin et al [65] show that recently-refreshed rows have more charge, and propose a mechanism (NUAT) to access the recently-refreshed rows with reduced latency (especially, tRCD/tRAS). Even though some of the observations in [65] are similar to ours, the approaches to leverage them are different.…”

Section: Related Workmentioning

confidence: 99%

“…Therefore, the two techniques are complementary and can potentially be combined for better performance. We note that (i) AL-DRAM has very little overhead compared to NUAT, and (ii) compared to [65], our work experimentally analyzes the dependence of DRAM latency on temperature and process variation in real DRAM chips.…”

Section: Related Workmentioning

confidence: 99%

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Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

187

328

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In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85• C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55• C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case.Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55• C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adaptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface.We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.

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Section: Related Workmentioning

confidence: 80%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Lee

Kim

Pekhimenko

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

187

328

View full text Add to dashboard Cite

show abstract

“…We compare to these schemes in the experiment section. In addition, schemes have also been proposed to reduce sensing time [15,49,55,14,46,34,9] and refresh overhead [17,50,42,10,40,36,6,8].…”

Section: Introductionmentioning

confidence: 99%

Restore truncation for performance improvement in future DRAM systems

Zhang

Childers

et al. 2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Scaling DRAM below 20nm has become a major challenge due to intrinsic limitations in the structure of a bit cell. Future DRAM chips are likely to suffer from significant variations and degraded timings, such as taking much more time to restore cell data after read and write access.In this paper, we propose restore truncation (RT), a lowcost restore strategy to improve performance of DRAM modules that adopt relaxed restore timing. After an access, RT restores a bit cell's voltage only to the level required to persist data to the next scheduled refresh rather than to the default full voltage. Because restore time is shortened, the performance of the cell is improved under process variations. We devise two schemes to balance performance, energy consumption, and hardware overhead. We simulate our proposed RT schemes and compare them with the state of the art. Experimental results show that, on average, RT improves performance by 19.5% and reduces energy consumption by 17%.

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Innovations in the Memory System

Balasubramonian

2019

Synthesis Lectures on Computer Architecture

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NUAT: A non-uniform access time memory controller

Cited by 63 publications

References 16 publications

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Restore truncation for performance improvement in future DRAM systems

Innovations in the Memory System

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