Innovations in the Memory System

Balasubramonian, Rajeev

doi:10.1007/978-3-031-01763-6

Cited by 4 publications

(2 citation statements)

References 191 publications

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“…The data shows the refresh penalty, 6 which is defined as the ratio of two key timing parameters used to govern refresh operations: t RF C , the duration of each refresh command, and t REF I , the time between consecutive refresh commands. The refresh penalty represents the average time that a DRAM rank (or bank) is unavailable for access due to refresh operations [208,[210][211][212][213]. We observe that the refresh penalty worsens from a median of 1.04% for 1 Kib chips to 2.05% for 16 Kib chips, then improves to 0.43% for 128 Mib chips, and finally worsens to a median of 4.48% (worst-case of 7.56% for DDR5 chips) for 16 Gib chips.This non-monotonic trend is due to the relative rates of improvement in DRAM access latency and storage capacity: access (and therefore, refresh) latencies stagnated around the introduction of 128 Mib chips while capacity improvements did not.…”

Section: Slowdown Of Generational Improvementsmentioning

confidence: 99%

“…Earlier DRAM chips refreshed rows using individual row accesses (e.g., RAS-only refresh), which result in comparable behavior for access and refresh operations. In contrast, newer DRAM chips aggressively refresh multiple rows per refresh operation (e.g., burst refresh), which differentiates refresh operations from normal row accesses [210,212,275]. 18 We omit the 2020 data point because 2020 shows a regression in CAS latency due to first-generation DDR5 chips, which we believe is not representative because of its immature technology.…”

Section: A2 Current Consumption Trendsmentioning

confidence: 99%

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Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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