NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes

Abstract

Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

“…[7][8][9] Thinning the channel thickness to form a nanosheet (NSH) structure effectively suppresses shortchannel effects and improves device performance due to enhanced on/off switching ability, 10,11 becoming a development trend of the transistor structure in very-large-scale integrated circuits. 12,13 However, the ultra-thin NSH channel makes it more complex and challenging to use ion implantation to modulate the device's threshold voltage (V TH ). The independent dual-gate (IDG) structure has been proposed to effectively modulate the V TH of the device and improve device performance by using an auxiliary gate to modulate the channel potential.…”