NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

Abstract

NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hocresistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

PSP-Equivalent Model for Double-Gate and Surrounding-Gate Field Effect Transistors for Circuit Simulation

“…and Q iD are calculated by means of Equations ( 10)- (14). Equation ( 11) depends on the terminal voltages through ψ sS and ψ sD and, in turn, on β, as is the case for the DGFET.…”

Ditch incorporated organic thin film transistor based organic all-p inverter: a novel approach

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Investigation of Trap Density Effect in Gate-All-Around Field Effect Transistors Using the Finite Element Method

“…In search of higher device performance and lower power consumption, new structures such as FinFETs [1] and Pi-gate [2], tri-gate [3], Omega-gated [4], and gate-all-around (GAA) MOSFETs [5] have been reported [6,7]. GAAFET structures are seen as the near-term future of integrated circuits as they provide highly electrostatic gate control [8]. GAAFET transistors have a gate-all-around structure, where the gate surrounds the semiconductor channel.…”