Novel zero side-etch process for &lt;1μm package redistribution layers

Nimbalkar, Pratik; Bhaskar, Pragna; Blancher, Christopher; Kathaperumal, Mohanalingam; Swaminathan, Madhavan; Tummala, Rao

doi:10.1109/ectc51906.2022.00343

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…This, however, results in a very rough surface (Ra > 200 nm), leading to challenges during lithography for achieving <5 µm critical dimensions. Therefore, there is an increased focus on the physical vapor deposition of metal seed layers for higher wiring density RDLs [21]. Layer-to-layer registration is a critical aspect affected by the CTE of the underlying dielectric.…”

Section: Fabrication and Processingmentioning

confidence: 99%

A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

Nimbalkar,

Bhaskar,

Kathaperumal

et al. 2023

Polymers

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The ever-increasing demand for faster computing has led us to an era of heterogeneous integration, where interposers and package substrates have become essential components for further performance scaling. High-bandwidth connections are needed for faster communication between logic and memory dies. There are several limitations to current generation technologies, and dielectric buildup layers are a key part of addressing those issues. Although there are several polymer dielectrics available commercially, there are numerous challenges associated with incorporating them into interposers or package substrates. This article reviewed the properties of polymer dielectric materials currently available, their properties, and the challenges associated with their fabrication, electrical performance, mechanical reliability, and electrical reliability. The current state-of-the-art is discussed, and guidelines are provided for polymer dielectrics for the next-generation interposers.

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Section: Fabrication and Processingmentioning

confidence: 99%

A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

Nimbalkar,

Bhaskar,

Kathaperumal

et al. 2023

Polymers

Self Cite

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“…To enable high-bandwidth signal processing between chiplets [ 10 ], several techniques, such as dual damascene processing, semi-additive processing (SAP) and polymer damascene processing, have been introduced. These techniques narrow the RDL trace width/pitch to as small as two microns [ 11 , 12 ] and even sub-microns [ 13 ]. To enhance the electricity transmission capacity, traces become thicker, with an aspect ratio of up to 4.2 [ 14 ], which is very different from traditional shell-like thin traces.…”

Section: Introductionmentioning

confidence: 99%

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Wu,

Wang,

et al. 2023

Micromachines

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The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.

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Organic Interposers Using Zero-Misalignment-Via Technology and Silicon Wafer Carriers for Large Area Wafer-Level Package Applications

Aleksov,

Talukdar,

Strong

et al. 2024

2024 IEEE 74th Electronic Components and Technology Conference (ECTC)

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Novel zero side-etch process for <1μm package redistribution layers

Cited by 4 publications

References 20 publications

A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Organic Interposers Using Zero-Misalignment-Via Technology and Silicon Wafer Carriers for Large Area Wafer-Level Package Applications

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