A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

Nimbalkar, Pratik; Bhaskar, Pragna; Kathaperumal, Mohanalingam; Swaminathan, Madhavan; Tummala, Rao R.

doi:10.3390/polym15193895

Cited by 9 publications

(2 citation statements)

References 62 publications

(74 reference statements)

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“…A micro bump of Cu post formed on LSI side and reduced amount of solder as shown in Fig. 3 has been used [2,3]. Since it has become difficult to connect a large number of bumps of an LSI chip to a motherboard, organic package substrates with narrower pitch pad and finer wiring and Si interposers manufactured by LSI back-end process technology have come to be used.…”

Section: D Packagingmentioning

confidence: 99%

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Recent Trend of Advanced LSI Packaging: Introduction for application of polymers

Ueno

2023

J. Photopol. Sci. Technol.

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Recent trends in Advanced LSI Packaging for heterogeneous integration are described. 2D package also called MCM (Multi Chip Module), FOWLP (Fan-Out Wafer Level Packaging) which has been applied to smartphones, 2.5D package using silicon chip as an interposer, chip embedded package which compensates for the shortcomings of the 2D and 2.5D package, and the 3D package which has recently gained great attention, are discussed. While it is becoming more difficult to improve performance by shrinkage of critical feature size and scaling rules, the proposed the concept of chiplets has led package technology to play a role in further improving the performance of LSIs.

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Section: D Packagingmentioning

confidence: 99%

“…Under such circumstances, heterogeneous integration combined with 2.5D, 3D packages using KGD (Known Good Die) which is selected good dies manufactured by good yield processes, and FOWLP (Fan-Out Wafer Level Packaging), etc. have been intensively developed [2,3,4].…”

Section: Introductionmentioning

confidence: 99%

Recent Trend of Advanced LSI Packaging: Introduction for application of polymers

Ueno

2023

J. Photopol. Sci. Technol.

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Strong Adhesion of Electroless Plated Copper by Optimizing Lamination Temperature of Epoxy Composite Film for Advanced Chip Packaging Substrates

Luo,

Yu,

et al. 2024

Adv Eng Mater

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Semi‐additive Process (SAP) is a pivotal technique for fabricating integrated circuit (IC) packaging substrates, achieving fine line/space resolution below 20 μm. The adhesion strength between the epoxy composite dielectric layer and electroplated copper is critical for ensuring the long‐term service reliability of high‐performance substrates. Herein, an epoxy composite film suitable for SAP is deposited with copper layer via electroless plating followed by electroplating. The effects of lamination and pre‐curing temperatures in SAP on the butter layer thickness, desmear weight, surface roughness (Ra), and adhesion strength of the plated copper are systematically investigated. The desmear weight decreases with the rising of lamination temperature attributed to the increased butter layer thickness. The lamination temperature is demonstrated to be one of the most influential factors in determining the adhesion strength between the plated copper and the epoxy composite. A high and stable peel strength exceeding 6.0 N/cm is achieved under the circumstance of a low Ra of merely 0.95 μm, indicating significant potential for these epoxy composite films in the fabrication of fine‐line and high‐density packaging substrates.This article is protected by copyright. All rights reserved.

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Structure, mechanical, and dielectric properties of polypropylene blended with ethylene and propylene‐based elastomers

Azrin,

Ahmad,

Lau

et al. 2024

J of Applied Polymer Sci

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Polypropylene (PP) has been widely researched in power cable insulation due to its excellent resistance against high temperatures and high voltages. Since PP is too stiff for power cable extrusion, elastomers have been blended with PP to improve its stiffness. Although effects of elastomers on electro‐mechanical properties of PP have been widely studied, fundamental issues governing changes in dielectric properties of PP/elastomer blends have yet to be fully understood. This paper therefore reports on the properties of PP blended with ethylene‐based elastomer (EBE) and propylene‐based elastomer (PBE) by correlating their structural, mechanical, and dielectric investigations with respect to elastomer types and contents. The results show that blending increasing amounts of EBE and PBE improves mechanical flexibility of PP, with Young's modulus reduces by 53% at 40 wt% of elastomer content. Morphology‐wise, PBE demonstrates better compatibility with PP and less disrupted crystallinity compared to EBE. Furthermore, PP/PBE has better breakdown performance over PP/EBE, albeit that their breakdown strengths reduce with increasing elastomer contents. Specifically, direct current breakdown strength of PP/PBE reduces by only 21% at 40 wt% of PBE loading compared to 31% at equivalent EBE loading. Potential mechanisms governing breakdown changes are discussed with structural, mechanical, and dielectric interpretations.

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A Review of Polymer Dielectrics for Redistribution Layers in Interposers and Package Substrates

Cited by 9 publications

References 62 publications

Recent Trend of Advanced LSI Packaging: Introduction for application of polymers

Recent Trend of Advanced LSI Packaging: Introduction for application of polymers

Strong Adhesion of Electroless Plated Copper by Optimizing Lamination Temperature of Epoxy Composite Film for Advanced Chip Packaging Substrates

Structure, mechanical, and dielectric properties of polypropylene blended with ethylene and propylene‐based elastomers

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