Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication

Flötgen, Christoph; Razek, Nasser; Dragoi, Viorel; Wimplinger, Markus

doi:10.1149/06405.0103ecst

Cited by 17 publications

(17 citation statements)

References 3 publications

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“…Wafer bonds from identical prime Si wafers with a 200 mm diameter were fabricated at room temperature using EVG's recently presented EVG580 ComBond machine-a high vacuum wafer bonding system. 8 The ComBond features a central handling cluster with attached modules for plasma surface activation, wafer flipping, and wafer bonding. Wafer transfer between the respective modules is fully automated with typical transfer times in the range of a minute.…”

Section: Methodsmentioning

confidence: 99%

Electrical properties of Si-Si interfaces obtained by room temperature covalent wafer bonding

Jung

Zhang

Dasilva

et al. 2018

Journal of Applied Physics

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We study covalent bonds between p-doped Si wafers (resistivity $10 X cm) fabricated on a recently developed 200 mm high-vacuum system. Oxide-and void free interfaces were obtained by argon (Ar) or neon (Ne) sputtering prior to wafer bonding at room temperature. The influence of the sputter induced amorphous Si layer at the bonding interface on the electrical behavior is accessed with temperature-dependent current-voltage measurements. In as-bonded structures, charge transport is impeded by a potential barrier of 0.7 V at the interface with thermionic emission being the dominant charge transport mechanism. Current-voltage characteristics are found to be asymmetric which can tentatively be attributed to electric dipole formation at the interface as a result of the time delay between the surface preparation of the two bonding partners. Electron beam induced current measurements confirm the corresponding asymmetric double Schottky barrier like band-alignment. Moreover, we demonstrate that defect annihilation at a low temperature of 400 C increases the electrical conductivity by up to three orders of magnitude despite the lack of recrystallization of the amorphous layer. This effect is found to be more pronounced for Ne sputtered surfaces which is attributed to the lighter atomic mass compared to Ar, inducing weaker lattice distortions during the sputtering.

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Section: Methodsmentioning

confidence: 99%

Electrical properties of Si-Si interfaces obtained by room temperature covalent wafer bonding

Jung

Zhang

Dasilva

et al. 2018

Journal of Applied Physics

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“…The wafer bonding utilizes the covalent bonds to integrate wafers with flat and clean surfaces, as shown in Figure a. [ 54 ] The key techniques for wafer bonding of III–V with Si are chemo‐mechanical polishing (CMP) and subsequent surface‐activated bonding. CMP uses chemical and mechanical forces to polish the surfaces of III–V and Si wafers resulting in very smooth surfaces with a root‐mean‐square roughness below 0.5 nm.…”

Section: Physical Connectionmentioning

confidence: 99%

The Intermediate Connection of Subcells in Si‐based Tandem Solar Cells

Zhang,

Li,

et al. 2023

Small Methods

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Tandem solar cells are rationally designed and fabricated by stacking multiple subcells to achieve power conversion efficiency well above the Shockley‐Queisser (SQ) limit. There is a large selection pool for the subcell candidates, such as Si, III–V, Kesterite, Perovskite, and organic solar cells. A series of different combinations of these subcells have been successfully demonstrated in practical tandem solar cell devices. However, there has not been a systematic summary of how to connect subcells in a tandem solar cell using a practical, cost‐effective, and efficiency‐beneficial fashion. In this work, the connection manners of subcells within a tandem cell are classified into three main categories, performing sequential growth, using the physical connection, and applying an intermediate layer, focusing on systematical description of intermediate layers using different materials. The advantages and disadvantages of these connection methods and their applicability to tandem cell types are further elaborated using two typical example models, III–V/Si and Perovskite inclusive tandem cell devices. Eventually, this work can provide useful guidance on how to carry out a suitable intermediate connection in the design of tandem solar cells depending on the selected subcells and device structure.

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“…A novel low temperature wafer bonding technology was recently developed [5] and demonstrated for the monolithic integration of two 10 µm thick silicon layers onto a standard 775 µm thick Si wafer [6]. The introduction of such a CMOS-compatible wafer bonding process is of great interest for the development of pixel detectors.…”

Section: Jinst 11 P08016mentioning

confidence: 99%

“…A first step consists in removing the native oxide to minimize lattice damages in the underlying silicon bulk. Next, bonding is performed by pressing (0.06 M Pa) while heating the samples at temperatures between 200 • C and 300 • C [5].…”

Section: Jinst 11 P08016mentioning

confidence: 99%

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Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

et al. 2016

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In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations. K: Detection of defects; Detector modelling and simulations II (electric fields, charge transport, multiplication and induction, pulse formation, electron emission, etc); Models and simulations; Solid state detectors 1Corresponding author.

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Novel Surface Preparation Methods for Covalent and Conductive Bonded Interfaces Fabrication

Cited by 17 publications

References 3 publications

Electrical properties of Si-Si interfaces obtained by room temperature covalent wafer bonding

Electrical properties of Si-Si interfaces obtained by room temperature covalent wafer bonding

The Intermediate Connection of Subcells in Si‐based Tandem Solar Cells

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

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