Novel solutions to enable contact resistivity &lt;1E-9 Ω-cm<sup>2</sup> for 5nm node and beyond

Hung, R.; Khaja, Fareen Adeni; Hollar, K.; Rao, K. V.; Munnangi, Samuel Swaroop; Chen, Yongmei; Okazaki, Motoya; Huang, Yi‐Chiau; Li, Xuebin; Chung, Hua; Chan, Osbert; Lazik, C.; Jin, Miao; Zhou, Haili; Mayur, A. J.; Kim, Namsung; Yieh, Ellie

doi:10.1109/vlsi-tsa.2018.8403817

Cited by 5 publications

(3 citation statements)

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“…To transition to the higher dopant activation process, laser thermal annealing (LTA) can achieve and meet the requirements of a low thermal budget. The LTA is well applied in power devices extending the Si-based devices with μm-scale deep activation [ 13 , 14 , 15 ], CMOS logic, and 3D sequential integration for active area formation and source/drain activation [ 16 , 17 , 18 ]. However, LTA has been less studied for memory applications compared with these fields.…”

Section: Introductionmentioning

confidence: 99%

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

et al. 2023

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

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Section: Introductionmentioning

confidence: 99%

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

et al. 2023

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“…According to the International Roadmap for devices and systems (IRDS) assumption with regard to the source/drain contact resistance and hole sizes, when the technology node is reduced to 3 nm, the source and drain contact resistivity is expected to be less than * Authors to whom any correspondence should be addressed. 6.4 × 10 −9 Ω cm 2 [1]. To achieve such requirements, the basic principles of reducing the source/drain contact resistivity are lowering the Schottky contact barrier height and increasing the dopant activation concentration at the metal/semiconductor interface.…”

Section: Introductionmentioning

confidence: 99%

“…These methods have extremely high requirements for the thickness and uniformity controllability of the insertion layer. On the other hand, dopant segregation [3,4], the introduction of advanced annealing tools [5][6][7][8], a dopant interlayer [9], metal-induced activation [10,11] and metal silicide-induced activation [12][13][14] have been extensively studied to improve the activation concentration of impurities at the metal/semiconductor interface. In situ phosphorus-doped silcon using chemical vapor deposition techniques, which exceeds the solid solubility level, has been applied 2 × 10 21 cm 3 [15,16].…”

Section: Introductionmentioning

confidence: 99%

Low contact resistivity of Ti/TiN/Al for NiSi₂ on epitaxial Si:P structure at full low-temperature process below 450 °C

Sun¹,

Wang²,

Bi³

et al. 2021

Semicond. Sci. Technol.

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Combined with Ti/TiN/Al for ultra-thin NiSi 2 and in situ-doped Si:P, an ultra-low contact resistivity of 4.6 × 10 −9 Ω cm 2 was achieved under a low thermal budget (⩽450 • C). The in situ-doped Si:P layer was grown by molecular beam epitaxy at 350 • C with a high doping concentration of 1.2 × 10 21 cm −3 exceeding the solid solubility. On the Si:P substrate, ultra-thin NiSi 2 film of 12.8 nm was formed by low-temperature drive-in diffusion and alloying at 180 • C and 450 • C, respectively. The Ti/TiN/Al-NiSi 2 -Si:P scheme provides a solution to the dilemma between performance boosting and reliability degradation in advanced very-large-scale integration manufacturing technology. It can also be applied in future monolithic three-dimensional integration.

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Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations

Khaja

2019

MRS Advances

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As advanced CMOS scaling with FinFETs continues beyond the 10/7nm nodes, contact resistance (Rc) remains a dominant component affecting device performance. The FinFET Source/Drain (S/D) contact area has become smaller with fin pitch scaling, resulting in drastically increased Rc. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes, it is critical to continue to reduce contact resistivity (ρc) < 1.0x10-9 Ω.cm2 for both NMOS and PMOS. In this paper, we review the recent trends for ρc reduction for advanced CMOS devices and discuss approaches that have demonstrated reduction in ρc, such as in-situ heavily doped epitaxial films for S/D, advanced ion implantation and laser anneals. The implant techniques include pre-amorphization implants (PAI), dopant boosting implants, cryogenic (-100°C) implants for damage engineering and plasma doping (PLAD) for conformal doping of high aspect ratio (HAR) contacts. With such high levels of doping from epi and implants, advanced laser anneals are key for epitaxial regrowth and formation of metastable alloys for dopant supersaturation or segregation in top layers. Millisecond laser anneal (MSA) improves dopant activation and nanosecond laser anneal (NLA) permits superactivation, and both have become key enablers for ρc reduction. This paper also reviews two alternative contact approaches: dual silicide scheme and wrap-around contact (WAC), as potential pathways to further reduce Rc for advanced CMOS nodes.

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Novel solutions to enable contact resistivity <1E-9 Ω-cm² for 5nm node and beyond

Cited by 5 publications

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Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

Low contact resistivity of Ti/TiN/Al for NiSi₂ on epitaxial Si:P structure at full low-temperature process below 450 °C

Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations

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Novel solutions to enable contact resistivity <1E-9 Ω-cm2 for 5nm node and beyond

Cited by 5 publications

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Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

Low contact resistivity of Ti/TiN/Al for NiSi2 on epitaxial Si:P structure at full low-temperature process below 450 °C

Contact Resistance Improvement for Advanced Logic by Integration of Epi, Implant and Anneal Innovations

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Novel solutions to enable contact resistivity <1E-9 Ω-cm² for 5nm node and beyond

Low contact resistivity of Ti/TiN/Al for NiSi₂ on epitaxial Si:P structure at full low-temperature process below 450 °C