Novel sizing algorithm for yield improvement under process variation in nanometer technology

Choi, Seung Hoon; Paul, B.C.; Roy, Kaushik

doi:10.1145/996566.996695

Cited by 111 publications

(66 citation statements)

References 12 publications

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“…Early developments are known under the heading "statistical design" [12]. Problems for which specific variation-aware techniques have been proposed include transistor sizing [7], yield optimization [5] and voltage binning [46]. Insertion of circuit elements to compensate for variations of propagation delay has been considered for delays in clock distribution networks [33] and in arbitrary logic gates [44].…”

Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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“…There is a large body of literature dealing with process variations and yield especially at the circuit level [4], [3], [22], [5]. The yield of SRAM storage cells has also been the subject of several studies [15], [11].…”

Section: Related Workmentioning

confidence: 99%

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Koh¹,

Wong

Chen³

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-There has been much work on the next generation of memory technologies such as MRAM, RRAM and PRAM. Most of these are non-volatile in nature, and compared to SRAM, they are often denser, just as fast, and have much lower energy consumption. Using 3-D stacking technology, it has been proposed that they can be used instead of SRAM in large level 2 caches prevalent in today's microprocessors. However, one of the key challenges in the use of these technologies, such as MRAM, is their higher fault probabilities arising from the larger process variation, defects in its fabrication, and the fact that the cache is much larger. This seriously affect yield. In this paper, we propose a fault resilient set associative cache architecture which we called the salvage cache. In the salvage cache, a faulty cache block is sacrificed and used to repair faults found in other blocks. We will describe in detail the architecture of the salvage cache as well as provide results of yield simulations that show that a much higher yield can be achieved viz-a-viz other fault tolerant techniques. We will also show the performance savings that arise from the use of a large next-generation L2 cache.

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“…In [20,21] gate-sizing are based on the linear programming and non-linear programming technique respectively. In [22,23,24] gatesizing are based on the Lagrangian Relaxation technique. Other gate-sizing optimization algorithms techniques are proposed in [25,26,27,28].…”

Section: Introductionmentioning

confidence: 99%

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Rodríguez

Garcia-Gervacio

Leal

2018

IEICE Electron. Express

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It is known that process parameter variation degrades the performance of nanometer integrated circuits. Process variations reduce the maximum clock frequency operation of the chips. Diverse strategies have been proposed in the literature to overcome this issue, especially optimization algorithms (gate-sizing algorithms). However, convergence related problems have limited their use. In this work, a homotopy approach for the design of nanometer digital circuits tolerant to process variations is proposed. Two optimization strategies are developed in this work, the first based on the homotopy continuation method (HCM) and the second based on a modification of HCM, called in this work reboot homotopy continuation method (RHCM). Three logic paths were implemented to validate the algorithms. The optimization results obtained with the proposed strategies are compared with a Lagrange-Multipliers-based framework. Results obtained from HCM method are equivalent to the obtained with Lagrange Multipliers. On the other side, results obtained from the RHCM method are more accurate than the obtained with HCM and Lagrange Multipliers. Furthermore, the area used to implement the logic paths is lower when RHCM is applied. Moreover, the number of Newton-Rhapson iterations required to find the solutions are lower when RHCM is used; consequently, time computing is also lower.

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Novel sizing algorithm for yield improvement under process variation in nanometer technology

Cited by 111 publications

References 12 publications

Towards Variation-Aware Test Methods

Towards Variation-Aware Test Methods

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

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