Novel single layer fault tolerance RCA construction for QCA technology

Taheri, Zahra; Rezai, Abdalhossein; Rashidi, Hamid

doi:10.2298/fuee1904601t

Cited by 15 publications

(10 citation statements)

References 33 publications

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“…Many researchers have implemented various configurations using QCA [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21], to accomplish the sum and carry functions of a full adder. Few adders were developed using multilayer layers and some with coplanar layers.…”

Section: Related Work On Adders Using Qcamentioning

confidence: 99%

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Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis

Gudivada

Sudha

2020

SN Appl. Sci.

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Complementary metal oxide semiconductor (CMOS) is a low-power technology typically used in the efficient implementation of digital circuits. However, at nanodimensions, CMOS has problems due to its short channel effects and subthreshold leakage currents. These drawbacks can be overcome with quantum-dot cellular automata (QCA) which is one of the fastest nanotechnologies operated at THz rate. Thus, all digital circuits can now be implemented by QCA at the required nanoscale. This paper proposes a novel, energy-efficient and area-optimized 1-bit full adder design using QCA which provides efficient clocking, reduced cell count and reduced energy dissipation. The proposed design utilizes only 26 quantum cells in 0.02 µm 2 area and has a reduction of 8% in number of cells, 75% in delay and 4% in energy dissipation at 1 K compared to the existing works. This innovative full adder design is used to implement a 4 × 4 Baugh-Wooley multiplier. The simulation results of the multiplier observed on QCADesigner 2.0.3 tool validate that the Baugh-Wooley multiplier designed with the novel 1-bit full adder yields better performance in terms of 9% reduction in area, 17.4% reduction in quantum cells used and reduced power dissipation of 2.44nW.

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Section: Related Work On Adders Using Qcamentioning

confidence: 99%

“…Later in [15][16][17], the authors designed a 1-bit full adder and implemented a ripple carry adder using it. The cell counts of these three full adders are 47, 46 and 44, respectively.…”

Section: Related Work On Adders Using Qcamentioning

confidence: 99%

Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis

Gudivada

Sudha

2020

SN Appl. Sci.

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“…Basic devices in this technology consist of QCA cells, wire crossing and QCA logic gates. The fundamental unit in the QCA technology is the QCA cell that is comprised of a square with 4 quantum dots in corners [1,4]. It should be noted that each QCA cell has only two electrons that can tunnel through neighboring dots.…”

Section: Introductionmentioning

confidence: 99%

Design of novel multiplexer circuits in QCA nanocomputing

Rashidi

Rezai

2021

FACTA U EE

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Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilize 16 (0.01?m2), 96 (0.11?m2), and 286 (0.43?m2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%- 99% compared to the existing multiplexer circuits.

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“…Sum and carry outputs of a full adder are designed in different layers and then this full adder is utilized for making the 4‐bit RCA 17 . A fault‐tolerant 3‐input majority gate was proposed and used for development of 1‐bit full adder and 4‐bit RCA 18 . A novel structure for D‐flip‐flop was developed and further utilized for 3‐bit serial input serial output shift register 19 .…”

Section: Introductionmentioning

confidence: 99%

“…17 A fault-tolerant 3-input majority gate was proposed and used for development of 1-bit full adder and 4-bit RCA. 18 A novel structure for D-flip-flop was developed and further utilized for 3-bit serial input serial output shift register. 19 A modified D-flip-flop was developed and used for 2, 3, 4, and 5-bit coplanar counter circuits.…”

Section: Introductionmentioning

confidence: 99%

Optimal design for digital comparator using QCA nanotechnology with energy estimation

Sharma

2020

Int J Numerical Modelling

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Quantum‐dot cellular automata (QCA) is a transistor‐less technology to implement the nanoscale circuit designs. QCA circuits are fast, highly dense and dissipate less energy as compared to widely used complementary metal oxide semiconductor (CMOS) technology. In this paper, a novel structure for digital comparator using QCA nanotechnology is proposed. Digital comparator is a basic and important module in central processing unit which compares two binary numbers. The proposed digital comparator is optimal, single layered with 0.50 clock latency and containing only 26 QCA cells. The proposed digital comparator is compared for the different performance metrics with the existing digital comparators. The calculations for energy dissipation are provided using QCA Designer‐E and QCA Pro tools. The proposed coplanar digital comparator is designed with minimum QCA cells which reduces the total cell area, total covered area and cost. Total cell area, total covered area and cost for the proposed digital comparator are 0.008 μm2, 0.023 μm2 and 0.006 respectively. Results show that energy dissipation for the proposed design is very less therefore, proposed digital comparator is energy efficient.

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Novel single layer fault tolerance RCA construction for QCA technology

Cited by 15 publications

References 33 publications

Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis

Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis

Design of novel multiplexer circuits in QCA nanocomputing

Optimal design for digital comparator using QCA nanotechnology with energy estimation

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