Novel redundant logic design for noisy low voltage scenarios

Garcia-Leyva, Lancelot; Calomarde, Antonio; Moll, Francesc; Rubio, Antonio

doi:10.1109/lascas.2013.6519010

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…In recent years, there have been several efforts to address the design of thermal-noise-tolerant circuit architectures [5,6,13,16]. All these works modeled the thermal noise by scaling the noise standard deviation up to a value that would allow a SET to be observed more easily in the logic circuits.…”

Section: Background and Related Workmentioning

confidence: 99%

A fast simulator for the analysis of sub-threshold thermal noise transients

Donato

Bahar

Patterson

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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The gate length of CMOS transistors is continuing to shrink down to the sub-10nm region and operating voltages are moving toward near-threshold and even sub-threshold values. With this trend, the number of electrons responsible for the total charge of a CMOS node is greatly reduced. As a consequence, thermal fluctuations that shift a gate from its equilibrium point may no longer have a negligible impact on circuit reliability. Time-domain analysis helps understand how transient faults affect a circuit and can guide designers in producing noise-resistant circuitry. However, modeling thermal noise in the time-domain is computationally very costly. Moreover, small fluctuations in electron occupation introduce time-varying biasing point fluctuations, increasing the modeling complexity. To address these challenges, this paper introduces a new approach to modeling thermal noise directly in the time domain by developing a series of stochastic differential equations (SDE) to model various transient effects in the presence of thermal noise. In comparisons to SPICE-based simulations, our approach can provide 3 orders of magnitude speedup in simulation time, with comparable accuracy. This simulation framework is especially valuable for detecting rare events that could translate into fault-inducing noise transients. While it is computationally infeasible to use SPICE to detect such rare events due to thermal noise, we introduce a new iterative approach that allows detecting 6σ events in a matter of a few hours.

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Section: Background and Related Workmentioning

confidence: 99%

A fast simulator for the analysis of sub-threshold thermal noise transients

Donato

Bahar

Patterson

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…Reference [26] discusses a novel logic redundancy method called gate level information flow tracking, which consumes three times the area of the original circuit. Reference [27] also presented a new logic redundancy method called turtle logic, which primarily addresses the design of digital circuits to cope with noisy scenarios for operation under ultralow supply voltages (i.e. the subthreshold regime).…”

Section: Introductionmentioning

confidence: 99%

Redundant logic insertion and fault tolerance improvement in combinational circuits

Balasubramanian

Naayagi

2017

2017 International Conference on Circuits, System and Simulation (ICCSS)

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Abstract-This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared.

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“…Request permissions from permissions@acm.org. [13] or Turtle Logic [9] have been proposed for mitigating the effects of noise. While there are many potential sources of noise, from current noise due to charge trapping in transistors to crosstalk voltage noise, in this paper we will focus on thermal noise as a fundamental, technology-independent noise source that has a clear statistical description.…”

Section: Introductionmentioning

confidence: 99%

Design of Error-Resilient Logic Gates with Reinforcement Using Implications

Han

Donato

Bahar

et al. 2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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Operating circuits in the sub-threshold region can save power, but at the cost of higher susceptibility to noise. This paper analyzes various gate-level error-mitigation designs appropriate for sub-threshold circuits. Previous works have proposed a modified version of the Schmitt trigger gate that uses logic implications to reinforce correct functional behavior. However, the increased error resilience requires increased area, delay, and power overhead. To address these shortcomings, we introduce two alternative and less costly approaches to reinforcing correct logic behavior via implications. In addition, to provide more flexibility in implication selection, we consider not just simple implications that reinforce relationships between two signals, but also more complex 3-signal implications within the circuit. Our simulation results demonstrate that these alternative gate structures can outperform the Schmitt trigger version as long as the noise on the reinforcement signals themselves is sufficiently low.

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Novel redundant logic design for noisy low voltage scenarios

Cited by 4 publications

References 5 publications

A fast simulator for the analysis of sub-threshold thermal noise transients

A fast simulator for the analysis of sub-threshold thermal noise transients

Redundant logic insertion and fault tolerance improvement in combinational circuits

Design of Error-Resilient Logic Gates with Reinforcement Using Implications

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