Novel process to pattern selectively dual dielectric capping layers using soft-mask only

Schram, T.; Kubicek, Stefan; Röhr, E.; Brus, S.; Vrancken, C.; Chang, Shu Chiuan; Chang, V.S.; Mitsuhashi, R.; Okuno, Y.; Akheyar, A.; Cho, H.-J.; Hooker, J.C.; Paraschiv, Vasile; Vos, Rita; Sebai, Farid; Ercken, Monique; Kelkar, Prasad; Delabie, A.; Adelmann, Christoph; Witters, T.; Ragnarsson, L.-Å.; Kerner, C.; Chiarella, T.; Aoulaiche, M.; Cho, Moonju; Kauerauf, T.; Meyer, K. De; Lauwers, A.; Hoffmann, T.; Absil, P.; Biesemans, S.

doi:10.1109/vlsit.2008.4588557

Cited by 13 publications

(13 citation statements)

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“…From Eqs. (47), (48), and ( 49), we find that (50) where V TH (= V TH7 +V TH4 −V TH6 −V TH5 ) is the difference between the threshold voltages of transistors M 4 -M 7 . The value of V TH depends on the transistor sizes [28], [29].…”

Section: Current References Consisting Of Subthreshold Mosfetsmentioning

confidence: 82%

Solid State Circuits Technologies

Swart¹

2010

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he continued as collaborating professor at FEEC/UNICAMP. His experience is in the field of Electrical Engineering, with emphasis in materials and semiconductor devices, mainly on the following subjects: Si and GaAs integrated circuit technologies, CMOS, HBT, thin films, plasma etching and nanoelectronics. He was president of the Brazilian Microelectronics Society for two terms. He was member of CA-EE of CNPq for two terms and also member of the Deliberative Council of CNPq for 4 years. He is Distinquished Lecturer, chair of EDS Subcommittee for Regions/Chapters (SRC) for Region 9 and elected member of the Board of Governors of the Electron Device Society of IEEE. He is Fellow of IEEE.

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Section: Current References Consisting Of Subthreshold Mosfetsmentioning

confidence: 82%

Solid State Circuits Technologies

Swart¹

2010

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“…1), and cleaning after gate patterning (Fig. 2), which is considered for implementation in a Single-Metal Dual-Dielectrics (SMDD) gate-first CMOS scheme (6,7). Furthermore, alternate cleaning methods and rinsing solutions were studied and developed to avoid the undesirable material loss.…”

Section: Introductionmentioning

confidence: 99%

“…Impact of Material Loss on nMOS V th Shift Figure 4 shows the shift of V th relative to the case without HK cap-dielectric layer for nMOS long channel devices. The test devices were fabricated in accordance with SMDD gate-first CMOS scheme (6). The V th shift linearly increased with La surface concentration of the La 2 O 3 layer inserted between HfO 2 and TiN/TaN metal gate, e.g.…”

Section: Introductionmentioning

confidence: 99%

New Wet Process Strategies for Reduced La₂O₃ and MgO₂ High-k Cap-dielectric Loss

Wada¹,

Vos²,

Claes³

et al. 2009

ECS Trans.

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Lanthanum oxide (La x O y ) and magnesium oxide (Mg x O y ) high-k cap-dielectrics have been used to modulate the effective work function for high-k/metal gate CMOS devices. The use of DIW during wet processing leads to unacceptable material loss due to the high solubility of materials. In this work, new rinsing procedures with pH-controlled and solvent-based solutions were evaluated in order to avoid material loss. It is validated that both pH-controlled (> pH 10) and solvent-based solutions achieve less than 1 Å of La 2 O 3 loss and solvent-based solutions can well be used on MgO 2 , providing less than 1 Å loss. Furthermore, no adverse affects, such as an increase in particle or surface roughness, were observed by applying the new rinsing procedures.

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“…Additionally, a new resist application for direct soft-mask patterning of dielectric capping layers in HK/MG module has been evaluated to relieve the process complexity and the cost for 32nm logic device and future nodes. 2 As it is the goal to run implant levels using the most cost effective process, design rule scaling for these levels should allow making full use of a cost effective toolset, as long as device characteristics meet their targets. However, tolerance limits to control CD and overlay are getting tighter, because process budgets have been much harder to be achieved along with aggressive requirements for smaller device.…”

Section: Introductionmentioning

confidence: 99%

Message to the undecided: using DUV dBARC for 32 nm node implants

Lee

Popova²,

Rolick³

et al. 2009

Advances in Resist Materials and Processing Technology XXVI

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In recent years, implant (block) level lithography has been transformed from being widely viewed as non-critical into one of the forefronts of material development. Ever-increasing list of substrates, coatings and films in the underlying stack clearly dictates the need for new materials and increased attention to this challenging area. Control of the substrate reflectivity and critical dimension (CD) on topography has become one of the key challenges for block level lithography and is required in order to meet their aggressive requirements for developing 32nm technology and beyond.The simulation results of wet-developable bottom anti-reflective coating (dBARC) show better reflectivity control on topography than the conventional top anti-reflective materials (TARCs), and make a convincing statement as to viability of dBARC as a working solution for block level lithography. 1 Wet-developable BARC by definition offers substrate reflectivity and resist adhesion control, however there is a need to better understand the fundamental limitations of the dBARC process in comparison to the TARC process. In addition, some specific niche dBARC applications as facilitating adhesion to challenging substrates, such as capping layers in the high-k metal gate (HK/MG) stack, can also be envisioned as most imminent dBARC applications. 2 However, most of the engineering community is still indecisive to use dBARC in production, bound by uncertainties of the robustness and lack of experience using dBARC in production.This work is designed to inspire more confidence in the potential use of this technology. Its objective is to describe testing of one of dBARC materials, which is not a photosensitive type, and its implementation on 32nm logic devices. The comparison between dBARC and TARC processes evaluates impacts of dBARC use in the lithographic process, with special attention to OPC behavior and reflectivity for controlling CD uniformity. This work also shows advantages and future challenges of dBARC process with several 248nm and 193nm resists on integrated wafers, which have shallow trench isolation (STI) and poly gate pattern topography.

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Novel process to pattern selectively dual dielectric capping layers using soft-mask only

Cited by 13 publications

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Solid State Circuits Technologies

Solid State Circuits Technologies

New Wet Process Strategies for Reduced La₂O₃ and MgO₂ High-k Cap-dielectric Loss

Message to the undecided: using DUV dBARC for 32 nm node implants

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Novel process to pattern selectively dual dielectric capping layers using soft-mask only

Cited by 13 publications

References 0 publications

Solid State Circuits Technologies

Solid State Circuits Technologies

New Wet Process Strategies for Reduced La2O3 and MgO2 High-k Cap-dielectric Loss

Message to the undecided: using DUV dBARC for 32 nm node implants

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New Wet Process Strategies for Reduced La₂O₃ and MgO₂ High-k Cap-dielectric Loss