Novel Parity-Preserving Designs of Reversible 4-Bit Comparator

Qi, Xianbiao; Fu-long, Chen; Wang, Hong-Tao; Sun, Yunxiang; Guo, Liangmin

doi:10.1007/s10773-013-1904-9

Cited by 6 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Two designs for a 4-bit fault tolerant reversible comparator were proposed [10]. The first design was based on the conventional approach and equations were derived from the truth table.…”

Section: B Parity Preserving Design Of Reversible 4-bit Comparatormentioning

confidence: 99%

“…This paper presents the design of n-bit reversible fault tolerant comparator. There are a few reversible comparators [6,7,8,9,10,11] but with number of garbage outputs being on the higher side. The proposed design outperforms the previous designs [8,10] in terms of garbage outputs and constant inputs.…”

Section: Introductionmentioning

confidence: 99%

“…The fault tolerant reversible gates which are utilized in this paper are Feynman-double gate (F2G) [5], NFT gate [12], MIG gate [13] and TVG gate [10] as shown in Table I. …”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Jayashree

Agarwal

Charan

et al. 2014

International Conference on Circuits, Communication, Control and Computing

View full text Add to dashboard Cite

Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.

show abstract

“…Two designs for a 4-bit fault tolerant reversible comparator were proposed [10]. The first design was based on the conventional approach and equations were derived from the truth table.…”

Section: B Parity Preserving Design Of Reversible 4-bit Comparatormentioning

confidence: 99%