Novel Designs of Quantum Reversible Counters

Qi, Xianbiao; Zhu, Haihong; Chen, Fulong; Jing-ci, Zhu; Zhang, Ziyang

doi:10.1007/s10773-016-3122-8

Cited by 7 publications

(3 citation statements)

References 16 publications

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“…-Design1 [15]: 35.71%, 5.88% and 61.11%, 37.5%, 18.75% in terms of CG, NGO, NCI, QC, number of CNOT gates, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…1) Design1: IN 2016 Xuemei Q [15] proposed a design of the reversible binary counter (Fig. 7) as follows: the TFF gate is equivalent to the TFG and FG gate according to the circuit below (Fig.…”

Section: B Design Of Reversible Binary Counter With Up/downmentioning

confidence: 99%

“…Our work will be divided into two parts the first concerns the design of a converter from decimal to BCD encoder based on a recent study design6 [14]: to modify it and improve the performance criteria compared to the latter and even to the five other studies design5 [14], design4 [13], design3 [12], design2 [12] and design1 [11]. The second concerns the design of a reversible binary counter based on a recent study design3 [17]by modifying it while keeping its same functionality and increasing the performance criteria compared to the latter and even to the two other studies design2 [16] and design1 [15]. The rest of this article is organized as follows: the second section presents the reversible gates concerned by this article by showing their performance criteria, namely the quantum cost that is deducted from the associated quantum implementation, and the hardware complexity.…”

Section: Introductionmentioning

confidence: 99%

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Optimized Design of a Converter Decimal to BCD Encoder and a Reversible 4-bit Controlled Up/Down Synchronous Counter

Andaloussi¹,

Brahim²,

Ghazi³

2021

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The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combinatorial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.

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“…-Design1 [15]: 35.71%, 5.88% and 61.11%, 37.5%, 18.75% in terms of CG, NGO, NCI, QC, number of CNOT gates, respectively.…”

Section: Resultsmentioning

confidence: 99%

Section: B Design Of Reversible Binary Counter With Up/downmentioning

confidence: 99%