Reversible logic has become increasingly important in the design of low power CMOS circuits, quantum computing and nanotechnology. In this article we work on recent sequential circuits namely RS Flip Flop JK Flop Flip Flop Flop Flip Flop Master Slave Flip Flop using some reversible gates FG (Feyman Gate), FRG (Fredkin Gate), NG (New Gate) , PG (Peres Gate), BJN (New BJN Gate), while modifying them to obtain new circuits keeping their same functionality and increasing their performances.
Reversible logic is becoming increasingly important in the design of low-power CMOS circuits, reversible circuits have given rise to what is called a quantum computer which is introduced by them with the aim of minimizing energy losses in the form of heat at the end of the lost bits and of performing more complex functions by taking into account certain criteria showing their performance, namely a number of gates ,a number of outputs garbage, a quantum cost, a delay and a hardware complexity. in this article, we will try to exploit a pre-existing article designing the asynchronous circuits in reversible mode, namely Circuit Implementation by latch using reversible logic gates and T Flip Flop sensitive to falling edge clock using reversible logic gates in order to obtain better results, by increasing their following performances quantum cost and the hardware complexity compared to our basic article.
The design of low consumption CMOS circuits, nanotechnologies and quantum computing has becomed more attached to the reversible logic. A set of gates have been recently exploited in reversible computer science for the design of certain circuits. Among them, we find the decoders. In this paper we have exploited a recent study making the design of the decoder 2 to 4, 3 to 8, and n to 2 n , our work aims to enhance the previous designs , by replacing some reversible gates by others while maintaining their functionality and improving their performance criteria namely the number of gates (CG), number of garbage outputs (NGO), number of constant inputs(NCI), Quantum cost (QC) and hardware complexity (HC), compared to our study of the base and other recent studies from which we have obtained remarkable results.
In the low power consumption, the reversible logic circuits are advantageous compared to the current ones, which is a good choice for the future design of computers. Among the characteristics of the reversible gates, the equality between the entries and the outputs, namely by the preservation of the parity of or circuits containing these gates have this same attribute. In this article we will base ourselves on a recent study of the FULL ADDER design to modify it and obtain improved results. Keyword -Quantum cost, number of garbage outputs, number of gates, delay, hardware complexity I. INTRODUCTION The technology of integrated circuit manufacturing has undergone remarkable development in recent years [1]. According to the Landauer law [2], each lost bit generates a quantity of heat KTLn2, to avoid this dissipation we will use quantum computation [3] and reversible computation [4] that we use a gate the same type (reversible). In this article, we will modify the FULL ADDER circuit based on a recent study [5] while keeping the same functionality and improving the following characteristics Number of gates, Hardware complexity, Quantum Cost, Delay and Number of garbage outputs.HNG [4] is our key reversible gate that we will use based on a recent study to design a
The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combinatorial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.