Novel methodology for mid-frequency delta-I noise analysis of complex computer system boards and verification by measurements

Garben, B.; McAllister, M.F.

doi:10.1109/epep.2000.895495

Cited by 9 publications

(3 citation statements)

References 2 publications

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“…A further reduction of the series inductance for capacitor groups can be achieved by connecting adjacent power pads and adjacent GND pads. Thus, the total series inductance for the 1-F capacitors was reduced from 0.87 nH in the 1999 G6 system implementation to 0.16 nH in the z900 implementation [11]. This reduction of the series inductance also reduced the parallel resonance of the capacitors.…”

Section: The Hierarchical Decoupling Strategymentioning

confidence: 95%

First- and second-level packaging for the IBM eServer z900

et al. 2002

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This paper describes the system packaging of the processor cage for the IBM eServer z900. This server contains the world's most complex multichip module (MCM), with a wiring length of 1 km and a maximum power of 1300 W on a glass-ceramic substrate. The z900 MCM contains 35 chips comprising the heart of the central electronic complex (CEC) of this server. This MCM was implemented using two different glass-ceramic technologies: one an MCM-D technology (using thin film and glass-ceramic) and the other a pure MCM-C technology (using glass-ceramic) with more aggressive wiring ground rules. In this paper we compare these two technologies and describe their impact on the MCM electrical design. Similarly, two different board technologies for the housing of the CEC are discussed, and the impact of their electrical properties on the system design is described. The high-frequency requirements of this design due to operating frequencies of 918 MHz for on-chip and 459 MHz for off-chip interconnects make a comprehensive design methodology and post-routing electrical verification necessary. The design methodology, including the wiring strategy needed for its success, is described in detail in the paper.

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Section: The Hierarchical Decoupling Strategymentioning

confidence: 95%

First- and second-level packaging for the IBM eServer z900

et al. 2002

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“…This feature is usually called Bfirst droop,[ and it arises from the interaction between the fairly small on-chip capacitance and the much larger capacitance of the discrete module capacitors located at the chip perimeter [7]. There is a second shallower minimum in chip voltage after approximately 40 ns (often called Bsecond droop[), which arises from the interaction between module capacitors and the capacitor groups on the PU card around the MCM.…”

Section: Voltage Stabilizationmentioning

confidence: 99%

Electronic packaging of the IBM System z196 enterprise-class server processor cage

Strach

Bosco²,

Köbel³

et al. 2012

IBM J. Res. & Dev.

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In this paper, we describe the first-and second-level system packaging structure of the IBM zEnterprise A 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power A blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

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“…At the module level, on printedcircuit boards, full-area conductive layers over thin laminates provide embedded capacitance for high-frequency decoupling [ 11, complemented by sometimes several thousands of capacitors for mid and lower frequency bypassing and decoupling [2]. Conductive plane pairs in printedcircuit boards (PCB) exhibit multiple resonances [3], which should be suppressed by proper damping of the structure [4], [5].…”

Section: Introductionmentioning

confidence: 99%

ARIES: using annular ring embedded resistors to set capacitor ESR in power distribution networks

Cyr

Novak²,

Biunno³

et al.

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)

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Power-distribution networks need to provide flat low impedance over a wide band. Bypass capacitors with different values, and capacitors and planes create resonance peaks, unless the capacitor parameters are selectedproperly. Distributed Matched Bypassing is used to create a smooth impedance profile. The ESR of ceramic capacitors is increased by adding embedded annular resistors in series to the Capacitors.

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Novel methodology for mid-frequency delta-I noise analysis of complex computer system boards and verification by measurements

Cited by 9 publications

References 2 publications

First- and second-level packaging for the IBM eServer z900

First- and second-level packaging for the IBM eServer z900

Electronic packaging of the IBM System z196 enterprise-class server processor cage

ARIES: using annular ring embedded resistors to set capacitor ESR in power distribution networks

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