Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

Novel Ultra-Low-Power Class AB CCII+ Based on Floating-Gate Folded Cascode OTA

“…The input stage of the FG-OTA consists of NMOST FG differential pairs M 1 and M 2 , where one of their gate terminals is biased on V DD whereas the second one is used to realize the conventional function of the CCII+. Transistors M 6 and M 7 provide a level shift function, and the cascoded current mirror comprised of M 8 , M 9 and M 9c provides a differential to single-ended conversion.…”

“…floating-gate differential pairs, folded cascode, cascoded current mirror technique, and class AB output OTA stage. Table 3 illustrates in detail the performance comparison of our proposed LV LP FG-CCII+ with other LV LP CCIIs and high-precision CCIIs based on conventional gate-driven MOST in [1,3,15,21,25], quasi-floating gate MOST in [13] and bulkdriven MOST in [9].…”

“…In general it should be noted that the main drawback of the QFG and BD techniques arises in feed-forward applications [9,18]. The voltage swing of the junction which implements R large for the QFG and the bulk-source voltage of the BD must be limited to 400 mV or even below in order to avoid forward biasing of the PN junction [9,13].…”

“…However, there are some implementations based on quasi-floating gate (QFG) [13] and bulk-driven (BD) technique [9]. Results reported in some references are as follows: [21] the supply voltage is ±0.75 V, power consumption is 1.62 mW, X-node parasitic impedance is 2.53 , and Znode parasitic impedance is 119.8 M ; [25] supply voltage ±1 V, X-node parasitic impedance 22.8 and Z-node parasitic impedance 12.563 k ; [11] supply voltage ±0.75 V, X-node parasitic impedance 6 ; [12] supply voltage ±1.5 V, X-node parasitic impedance 286 and Z-node parasitic impedance 45 M ; [15] supply voltage 1.5 V; [8] supply voltage ±1.5 V, X-node parasitic impedance 15 ; [3] supply voltage 3.3 V, X-node parasitic impedance 42 and parasitic output impedance at Z terminal 2.24 M ; [22] supply voltage ±3 V; [1] supply voltage ±0.75 V, X-node parasitic impedance 1.8 ; [13] the supply voltage is ±0.5 V, power consumption is 27 µW, X-node parasitic impedance is 1.5 , and Z-node parasitic impedance is 1.2 M ; [9] the supply voltage is ±0.4 V, power consumption is 27 µW, X-node parasitic impedance is 27 , and Z-node parasitic impedance is 0.89 M .…”

Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage

“…Recently, this technique has been used for design of basic building blocks of analog and digital integrated circuits (IC), e.g. operational amplifier [6], [7], current mirrors [8], [9], current converter [10], [11], operational transconductance amplifier (OTA) [6], [12], voltage follower [13], [14], voltage to current converter [15], voltage controlled oscillator [16], phase locked loop (PLL) [17], etc.…”