Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

Luo, Xiaorong; Wang, Yuangang; Deng, Hao; Fan, Jintao; Lei, Tianfei; Liu, Yong

doi:10.1109/ted.2009.2037372

Cited by 31 publications

(10 citation statements)

References 14 publications

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“…2, which is divided into NI and NII, and the Wlat is the lateral depletion width. And when Wlat satisfies Lm-1≤Wlat≤Lm (m=1, 2 … n, i=1, 2 … m), the surface electric field of NI will be obtained as (16).…”

Section: ( ) ( )mentioning

confidence: 99%

“…In order to improve the performance of lateral SOI high voltage devices, design researchers have proposed a variety of optimization schemes for new device structures: air partial SOI (APSOI) structure [11], single step buried oxide layer SOI (SBOSOI) structure [12], double step buried oxide layer SOI (BODSSOI) structure [13], P-type buried layer SOI (BPSOI) structure [14], variable low-k dielectric buried layer BPSOI (VLKD BPSOI) structure [15], and low-k dielectric buried layer PSOI (LK PSOI) structure [16]. Under the effect of electric field modulation [17], these changes in buried layer will introduce new electric field peaks on the surface of the drift region, which will make the surface electric field distribution more evenly and improve the performance of SOI LDMOS significantly.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

Duan

Xing

Dong

et al. 2020

IEEE J. Electron Devices Soc.

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The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

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Section: ( ) ( )mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

Duan

Xing

Dong

et al. 2020

IEEE J. Electron Devices Soc.

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“…Moreover, the first peaks are higher than the corresponding peaks at the drain end for both SOI and PSOI structures, implying that the RESURF effect is hardly to be perfectly achieved under small device dimensions and uniform doping drift region. Better RESURF can be achieved in devices of larger dimensions (Hu et al, 2012;Luo et al, 2008Luo et al, , 2010 or linear doping drift region (Guo, Li, & Zhang, 2006;Merchant, 1991;Shengdong, Sin, Lai, & Ko, 1999;Tadikonda et al, 2004), in which the surface electric fields at the source and drain ends are more symmetric and uniform. Figure 4(b).…”

Section: International Journal Of Electronics 39mentioning

confidence: 99%

“…>15 μm (Luo et al, 2010;Park et al, 2003;Tadikonda et al, 2004) and >100 μm (Luo et al, 2008). However, the tendency of device scaling down is irrefragable in semiconductor technology.…”

Section: Introductionmentioning

confidence: 99%

Thin-film LDMOS on partial SOI with improved breakdown voltage and suppressed kink effect

Wang

Chang

et al. 2013

International Journal of Electronics

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Thin-film (TF) lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOSFET or LDMOS) of small dimensions on partial silicon-on-insulator (PSOI) with improved breakdown voltage and suppressed kink effect is introduced and studied. The silicon window and field plate can modulate the surface electric field of silicon film and, thus, their design parameters can be adjusted to achieve optimal breakdown voltage. Moreover, the silicon window can also provide a conduction path from the thin silicon film to the substrate and prevent hole accumulation in the floating body of silicon-on-insulator (SOI) devices, which can consequently suppress the kink effect. Effects of the device parameters (e.g. location of the field plate, location of silicon window, and doping concentrations of the drift region, silicon window and substrate) that control the performance of TF PSOI LDMOS are carefully studied. Compared with the conventional TF SOI LDMOS of small dimensions, the simulation results show that this proposed TF PSOI LDMOS exhibits approximately 100% improvement on the breakdown voltage and entirely eliminates the kink effect.

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“…The main problem is low breakdown voltage and many structures are proposed to obtain high breakdown voltage [10][11][12].…”

Section: Introductionmentioning

confidence: 99%