Novel high-voltage power device based on self-adaptive interface charge

吴丽娟,; 胡盛东,; 张波,; 李肇基,

doi:10.1088/1674-1056/20/2/027101

Cited by 8 publications

(3 citation statements)

References 9 publications

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“…Table 1 shows characteristics of several structures. Compared to the structure with self-adaptive interface charge, [13] the conductance factor is more than doubled in the MHFC device. The conductance factor in shield trench device is less than half of the proposed device with the same BV, but it is very difficult to fabricate.…”

Section: -4mentioning

confidence: 99%

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New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

Li¹,

Li²,

Tang³

et al. 2015

Chinese Phys. B

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A new SOI power device with multi-region high-concentration fixed charge (MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer (BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.

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Section: -4mentioning

confidence: 99%

“…The conductance factor in shield trench device is less than half of the proposed device with the same BV, but it is very difficult to fabricate. [11] [13] 612 0.88 5 Double-sided trench [12] 796 1.56 20 Shield trench [11] 598 0.9 3…”

Section: -4mentioning

confidence: 99%

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

Li¹,

Li²,

Tang³

et al. 2015

Chinese Phys. B

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“…GaN, with a high saturation velocity at a high electrical field (υ sat ∼ 3×10 7 cm/s at 150 kV/cm), [1,2] a high critical electrical field (up to 3 MV/cm), a good thermal conductivity, [3] and epilayers grown on Si, [4,5] has been widely studied for applications in high-power and high-temperature devices, such as heterojunction field-effect transistors (HFETs). Compared with the conventional radio frequency (RF) AlGaN/GaN HFETs, [6−11] GaN metal-oxide-semiconductor fieldeffect transistors (MOSFETs) feature a large voltage sweep range, low gate leakage currents and circuit simplicity, hence they have attracted much attention lately.…”

Section: Introductionmentioning

confidence: 99%

A study of GaN MOSFETs with atomic-layer-deposited Al₂O₃as the gate dielectric

Xing¹,

Wang²,

Feng³

et al. 2012

Chinese Phys. B

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Accumulation-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited Al2O3 gate dielectrics are fabricated. The device, with atomic-layer-deposited Al2O3 as the gate dielectric, presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm, which are better than those reported previously with Al2O3 as the gate dielectric. Furthermore, the device shows negligible current collapse in a wide range of bias voltages, owing to the effective passivation of the GaN surface by the Al2O3 film. The gate drain breakdown voltage is found to be about 59.5 V, and in addition the channel mobility of the n-GaN layer is about 380 cm2/Vs, which is consistent with the Hall result, and it is not degraded by atomic-layer-deposition Al2O3 growth and device fabrication.

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A Novel Silicon-on-Insulator Super-Junction Lateral-Double-Diffused Metal-Oxide-Semiconductor Transistor with T-Dual Dielectric Buried Layers

Wu¹,

Zhang²,

Zhang³

et al. 2013

Chinese Phys. Lett.

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A novel silicon-on-insulator (SOI) high-voltage device of super-junction (SJ) lateral-double-diffused metal-oxidesemiconductor transistors (LDMOSTs) with T-dual dielectric buried layers (T-DBLs) is presented. The T-DBLs are formed by the first T-shaped dielectric layer and the second dielectric layer. A lot of holes are accumulated on the top interface of the second dielectric layer, which compensates for the charge imbalance of the surface N and P pillars, thus the substrate-assisted depletion (SAD) effect is eliminated in the new device. The electric field of the second dielectric buried layer, 𝐸 I2 , is enhanced by the interface charges, and the breakdown voltage 𝑉 breakdown is increased. 𝐸 I2 = 515 V/𝜇m is obtained in the T-DBL SOI SJ. The 𝑉 breakdown of the new device is increased from 124 V of the conventional SOI SJ to 302 V with a 15 𝜇m length drift region. The specific on-resistance (𝑅on,sp) of the T-DBL SOI SJ is only 0.00865 Ω•cm 2 and the FOM (FOM = 𝑉 2 breakdown /𝑅on,sp) is 10.54 MW/cm 2 .

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Novel high-voltage power device based on self-adaptive interface charge

Cited by 8 publications

References 9 publications

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A study of GaN MOSFETs with atomic-layer-deposited Al₂O₃as the gate dielectric

A Novel Silicon-on-Insulator Super-Junction Lateral-Double-Diffused Metal-Oxide-Semiconductor Transistor with T-Dual Dielectric Buried Layers

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Novel high-voltage power device based on self-adaptive interface charge

Cited by 8 publications

References 9 publications

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A study of GaN MOSFETs with atomic-layer-deposited Al2O3as the gate dielectric

A Novel Silicon-on-Insulator Super-Junction Lateral-Double-Diffused Metal-Oxide-Semiconductor Transistor with T-Dual Dielectric Buried Layers

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A study of GaN MOSFETs with atomic-layer-deposited Al₂O₃as the gate dielectric