Novel, high-performance polysilicon heterostructure TFTs using P-I-N source/drains

Abstract

We have demonstrated improvement of ON/OFF ratio and reduction of leakage current in polysilicon thin film transistors by (A) inserting a thin polycrystalline silicon-germanium layer in the middle of the channel to confine the carriers away from the highly defective polysilicodsilicon-dioxide interface by using the bandgap offset in the valence band, and (B) introducing nearintrinsic regions at the source/drain ends of the channel to reduce the peak lateral electric field in the channel, thereby reducing field emission through grain boundaries.

A p-channel poly-Si/Si/sub 1-x/Ge/sub x//Si sandwiched conductivity modulated thin-film transistor

“…However, due to the poor interface between the poly-Si Ge channel and the SiO gate dielectric, only devices with poor on-state and leakage performance were obtained. To alleviate this problem, a thin layer of poly-Si is introduced between the poly-Si Ge channel and the SiO gate dielectric to provide a better interface [6], [7]. However, the leakage current of the devices was still high compared to that of the poly-Si counterpart due to the fact that the poly-Si Ge active layer used has a smaller band gap [7].…”