Novel Hardware Implementation of Modified RC4 Stream Cipher for Wireless Network Security

Abstract

This paper presents novel hardware implementation of modified RC4 stream cipher for wireless network security. The Modified RC4 algorithm proposes two changes in conventional RC4 stream cipher algorithm, one in Key Scheduling Algorithm (KSA) stage and other in Pseudorandom Generation Algorithm (PRGA) stage. This modification in KSA removed many weakness and produces random states, so that it will hard to identify any nonuniformity in the permutation after KSA. The other modification in PRGA has destroyed relation between internal states of S-boxes, which is base of many attacks on RC4. The proposed architecture uses variable key length from 1 byte to (256+256+8) 520 bytes but previous designs support maximum key length of 256 bytes. This architecture achieved throughput of 63.449 Mbps at a clock frequency of 190.349 MHz independent of key length. The system was implemented in hardware by using VHDL language and Xilinx FPGA device.