Novel explicit pulse-based flip-flop for high speed and low power SoCs

Abstract

Abstract:In this paper, novel explicit pulse-based flip-flop having dual precharge nodes is presented. Dual precharging can minimize the parasitic capacitance of each precharge node by making output transistors driven separately, resulting in high-speed and low-power operation. The switching speed is further improved by avoiding the use of stacked transistors for driving the output load. Pulse-based nature of the proposed flip-flop also provides a negative setup time and minimizes the effects of clock skew. The proposed flip-flop was designed using a 0.18 um CMOS technology, whose comparison results indicate that the flip-flop achieves up to 32% power reduction with 11% speed improvement. They also indicate that the power-delay product is decreased by up to 39% compared to conventional pulse-based flipflops. Keywords: dual precharging, pulsed flip-flop, low power, high speed Classification: Integrated circuits References[1] V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of masterslave and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-540, April 1999. Solid-State Circuits, vol. 34, no. 5, pp. 712-716, May 1999. [4] J. Tschanz, S. Narendra, S. Zhanping Chen Borkar, and M. Vivek De Sachdev, "Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors,"

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

“…The dual-edge latching operation is implemented either by generating a latch trigger pulse at both clock edges or by utilizing two-phase clocked flip-flops. For example, in [9,10,11,12,13,14], triggering pulses are explicitly generated with a pulse-generating circuit. Since a separate pulse generator and latch are required, the area overhead for these DET-FFs is significant.…”