Novel designs for digital gates based on single electron devices to overcome the traditional limitation on speed and bit error rate

Sharifi, Mohammad Javad; Ahmadian, Mehdi

doi:10.1016/j.mejo.2017.12.012

Cited by 13 publications

(6 citation statements)

References 22 publications

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“…In the literature, some SET logic gates have already been proposed [12,13,14,15,16,17,2,18,19,20,21]. In particular, different circuit architectures of SET-NANDs can be found in [2,18,19].…”

Section: Set Nand/nor Programmable Logic Gatementioning

confidence: 99%

Digital Circuits and Systems based on Single-Electron Tunneling Technology

Guimarães

Câmara

2021

JICS

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In this work, digital circuits and systems based on single-electron tunneling technology will be presented and analyzed. A simple design methodology will be proposed using a programmable single-electron NAND/NOR gate as a building block. Aspects such as operating temperature, noise, and charge fluctuations will be discussed. SET devices can reach ultra-low power consumption and high frequencies during operation. Although there are already many digital SET circuits and systems previously proposed and studied, there are few works about design methodology for SETs. This study shows a proposal for designing combinational and sequential singleelectron circuits aiming at systems design. In the end, this work reinforces the use of single-electron technology as a possible large scale device in the future.

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Section: Set Nand/nor Programmable Logic Gatementioning

confidence: 99%

Digital Circuits and Systems based on Single-Electron Tunneling Technology

Guimarães

Câmara

2021

JICS

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“…e complementary metal oxide semiconductor (CMOS) technology has many defects, such as short channel effect and high power consumption; it cannot, therefore, continue to follow Morrie's law by increasing the number of devices per chip [1]. It creates the need for nanoscale devices, with high-performance rates and low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Nanotechnology QCA Geometric Greedy Router

Touil

Gassoumi

Mtibaa

2021

Journal of Electrical and Computer Engineering

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This paper presents an optimized geometric greedy router (GGR) based on quantum dot cellular automata (QCA) technology. The proposed structure of GGR is based on a spanning tree of the network. This type of communication does not require an IP address. It uses only local information and can be used in many communication devices. In this paper, we first describe the principal components of the router and then we present their QCA architecture. The QCA technology is the most likely alternative to replace conventional circuits (CMOS) due to their very low power consumption and high processing speed. To consider integration with other complex circuit, we have utilized QCA clock-phase-based technique for the proposed design architecture. The results obtained using the QCA designer tool exhibit the superiority of the presented architecture over the existing designs. The proposed structure shows a reduction of 30% reduction in occupied space. The power dissipation rate of the proposed design is analyzed by QCAPro tool to approve its reliability.

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“…Complementary Metal Oxide Semiconductor (CMOS) technology faces major problems such as short channel effects [1], high current leakage, decreasing gate control and high lithography costs, etc., when scaled down near to nanometers [1]. Scientists and researchers seek to find alternatives to the traditional CMOS process [2]- [4], to overcome the above mentioned problems.…”

Section: Introductionmentioning

confidence: 99%

“…To find replacements for the CMOS technology, many devices and techniques are being introduced and evaluated by researchers, such as Spin-wave architecture, Single-electron devices, Quantum Computing etc. [2], [3]. Among the existing new techniques, CNTFET is one of the demonstrated alternatives to CMOS transistors, which operates satisfactorily [5], [6].…”

Section: Introductionmentioning

confidence: 99%

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

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The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

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Novel designs for digital gates based on single electron devices to overcome the traditional limitation on speed and bit error rate

Cited by 13 publications

References 22 publications

Digital Circuits and Systems based on Single-Electron Tunneling Technology

Digital Circuits and Systems based on Single-Electron Tunneling Technology

Design and Implementation of Nanotechnology QCA Geometric Greedy Router

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

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