Novel design and reliability assessment of a 3D DRAM stacking based on Cu-Sn micro-bump bonding and TSV interconnection technology

Li, Cao; Wang, Xuefang; Chen, Mingxiang; Zhou, Shengjun; Lv, Yaping; Liu, Sheng

doi:10.1109/ectc.2013.6575831

Cited by 2 publications

(2 citation statements)

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“…In general, in order to improve the overall bonding strength of the connection interface, different kinds of bonding mediums, such as polymer adhesives and underfill materials, are used to form a hybrid bonding structure. Yet, in the TC test, for chip stacking modules, the significant mismatches of CTE between the bonding mediums and other materials may be a challenge [13]. In this paper, to better contrast the reliability of nanoporous bonding module and normal bonding module and exclude the influence of underfill or other materials, they are not utilized in the TC test.…”

Section: Thermomechanical Reliabilitymentioning

confidence: 96%

“…To build stronger interface, in [11] and [12], attention has been mostly focused on adding novel bonding mediums, such as polymer adhesives or underfill materials. Yet stronger overall bonding strength does not mean more reliable microjoints, because the significant mismatches of coefficient of thermal expansion (CTE) are a great challenge in thermal cycling and thermal shock environment [13]. Here, microbumps with nanoporous structure are formulated to improve the reliability of the microjoints, which is beneficial for copper-tin alloying in flip-chip bonding process due to its large contact area.…”

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confidence: 99%

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21-Layer 3-D Chip Stacking Based on Cu-Sn Bump Bonding

Wang

Song

et al. 2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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A 3-D chip-to-chip stacking technology is presented, in which several key techniques involving the wafer thinning process are integrated, through silicon via (TSV) etching and plating, redistribution layer formulation, and the flip chip chip bonding process. Nanoporous Cu-Sn microbump bonding technology is introduced, and a novel 3-D module-to-module bonding method is developed. Compared with the reported 3-D packaging technologies, a chip stacking module with more than 21 layers is obtained in the flip-chip stacking style. Each layer of the stacking module has an ultrathin thickness of 60-80 µm, and the pitch of the TSV is 200 µm. Such as bonding strength measurement, thermal cycling test and electrical measurement are implemented to evaluate the reliability of the chip stacking module. The results have shown that the presented 21-layer stacking module has a better tensile and shear strength, and preferable contact resistance, as well as over 1000 thermal cycles.Index Terms-3-D packaging, Cu-Sn bonding, multilayer stacking, nanoporous bump, through silicon via (TSV).

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Section: Thermomechanical Reliabilitymentioning

confidence: 96%

mentioning

confidence: 99%