21-Layer 3-D Chip Stacking Based on Cu-Sn Bump Bonding

Abstract

A 3-D chip-to-chip stacking technology is presented, in which several key techniques involving the wafer thinning process are integrated, through silicon via (TSV) etching and plating, redistribution layer formulation, and the flip chip chip bonding process. Nanoporous Cu-Sn microbump bonding technology is introduced, and a novel 3-D module-to-module bonding method is developed. Compared with the reported 3-D packaging technologies, a chip stacking module with more than 21 layers is obtained in the flip-chip stacking style. Each layer of the stacking module has an ultrathin thickness of 60-80 µm, and the pitch of the TSV is 200 µm. Such as bonding strength measurement, thermal cycling test and electrical measurement are implemented to evaluate the reliability of the chip stacking module. The results have shown that the presented 21-layer stacking module has a better tensile and shear strength, and preferable contact resistance, as well as over 1000 thermal cycles.Index Terms-3-D packaging, Cu-Sn bonding, multilayer stacking, nanoporous bump, through silicon via (TSV).

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