Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design

Chang, Y. H.; Chuang, Hao-Hsiang; Lu, Yi-Chang; Chiou, Yih-Peng; Wu, Tzong‐Lin; Chen, Peng-Shu; Wu, S.F.; Kuo, Tzu-Ying; Zhan, Cheng; Lo, Wei‐Chung

doi:10.1109/epeps.2012.6457884

Cited by 21 publications

(10 citation statements)

References 6 publications

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“…References [1][2][3] suggest using the relation between the inductance matrix and the capacitance matrix (per unit length) in a homogeneous medium in order to estimate the capacitance matrix of a TSV array…”

Section: Fig 2 Homogeneous Medium Model For Coupling Capacitance Extmentioning

confidence: 99%

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Coupling capacitance in through‐silicon vias: non‐homogeneous medium effect

et al. 2016

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To extract the coupling capacitance between any two neighbouring through-silicon vias (TSVs) in three-dimensional integrated circuits, most publications use the relation between the inductance matrix and the capacitance matrix (per unit length). However, this relation is based on a homogeneous surrounding medium assumption. It is shown that the previous assumption is inaccurate due to the fact that each TSV is actually surrounded by a non-homogeneous medium (silicon and silicon dioxide materials). The theory behind this claim is provided and validated using ANSYS Q3D. The percentage error in coupling capacitance between the Q3D extraction results and the homogeneous medium model results can reach 70%.

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Section: Fig 2 Homogeneous Medium Model For Coupling Capacitance Extmentioning

confidence: 99%

“…Problem statement: References [1][2][3] propose the following model to extract the coupling capacitance of two TSVs as shown in Fig. 2 C ox = pe o e ox h ln (r + t ox )/r…”

Section: Fig 2 Homogeneous Medium Model For Coupling Capacitance Extmentioning

confidence: 99%

Coupling capacitance in through‐silicon vias: non‐homogeneous medium effect

et al. 2016

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“…By assuming the aggressor TSV array as the multiconductor transmission line within silicon substrate and the victim TSV as the ground signal [19], the TSV-array inductance matrix [L Si ] is computed by applying the following formula: where P ij is the distance between aggressor TSV i and j and the victim is labeled 0. Note in this formula, unlike the 2-TSV model, not only the distances between aggressor and the victim are considered, but also the distances between aggressor are considered.…”

Section: B Multitsv Modelmentioning

confidence: 99%

“…The voltage waveforms of the aggressors are not affected much by the coupling. Previous work [19] used all of the coupling components between TSVs which is not a feasible solution in full-chip level. E.g., an array of 100 TSVs leads to more than 20 000 RC components in the model.…”

Section: B Multitsv Modelmentioning

confidence: 99%

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Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling

Peng

Song

Petranovic

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents a silicon effect-aware multiTSV model. Through-silicon-via (TSV) depletion region, silicon substrate discharging path and electrical field distribution around TSV neighbor are modeled and studied in full-chip design. Verification with field solver and full-chip TSV-to-TSV coupling analysis in both the worst case and the average case show this model is accurate and efficient. It is found that 3-D nets receive more noise than their 2-D counterparts due to TSV-to-TSV coupling. To alleviate this coupling noise on TSV nets, two new optimization methods are investigated. One way is to utilize guard rings around the victim TSV so as to form a stronger discharging path, an alternative approach is to adopt differential signal transmission to improve noise immunity. These techniques have been implemented on 3-D IC designs with TSVs placed regularly or irregularly. Full-chip analysis results show that our approaches are effective in noise reduction with small area overhead.

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