Novel Built-In Current-Sensor-Based $I_{\rm DDQ}$ Testing Scheme for CMOS Integrated Circuits

Hsu, Chun-Lung; Ho, Mean-Hom; Lin, Chih‐Feng

doi:10.1109/tim.2009.2013668

Cited by 16 publications

(2 citation statements)

References 18 publications

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“…Stress exerted on wordline has used to detect the defects in memory [17]. Variations in quiescent supply currents have used to detect the faults [18]. Deviations in the transient current are used for the detection of the faults at block level [19].…”

Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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The efforts in the semiconductor industry lead to the up-gradation of device size and performance of the devices. Extensive use of cache memory with significant size has become the requirement of most devices, applications, and gadgets. Advanced nanotechnology has resulted in scaled devices and more components with complex circuitry on system-on-chip. The memories are placed incredibly more profound in the die, and memory pins are not accessible readily, leading to more complications in testing the memories. The manufacturing of scaled devices is also a challenging task. A slight variation in doping concentration or process, supply voltage, temperature variations leads to faults in the memory. Advanced technology has increased the possibilities of occurrences of resistive defects in memories. For the smooth operation of systems with high reliability, it is essential to detect all the defects in the memory. In this paper, the detection of resistive defects is proposed at an early stage to increase the life span of the memory cells. Feeble cell detected at an early stage inhibits the more mutilation of the cells and improves memory reliability. An extensive range of defective values is used to analyze the proposed method to cover all positions of the defects in the cell. The proposed method detects the resistive defects with a minimum test time of 81.95μs for 4KB of the memory and contributes a negligible area overhead of 0.77%.

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Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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“…One of the used protection techniques is the addition of built-in current sensors, which detect faults by surveilling unexpected variations in the electrical current that supplies the memory blocks [11,24]. This technique can be improved by using a robust Error Correction Code (ECC), which is the principal objective of this paper.…”

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confidence: 99%

An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

et al. 2018

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As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.

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