An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

Abstract

As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

“…Extended Hamming is a Hamming code having one more parity bit that increases the code capacity to detect double errors and correct a single error, i.e., an SEC-DED code [20]. The parity bit can be either 0 or 1, depending on the parity type (i.e., even or odd).…”

“…The reliability analysis of this work is based on the works of Silva et al [20] and Argyrides et al [40]. We assume the following statements that were also assumed by [40]: (i) transients faults occur with a Poisson distribution, and (ii) bit faults are statistically independent.…”

CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC

“…The works [13] [16] describe that the 39-bit codeword of CLC is divided into four sets of bits: 16 (16,39) -16-bit data [16].…”

“…Depending on the results of the syndrome calculation, an action of the correction table is taken. To deal with these error patterns, [16] proposed the CLC Extended mode (CLC-E), which checks each line of the codeword twice, being a 2-step correction process. The CLC-E can correct all 3-bit adjacent errors, increasing the correction efficacy of the CLC Standard mode (CLC-S).…”

“…In [16], the authors presented new CLC versions that explore different structures of Extended Hamming for performing tradeoffs on synthesis cost reduction or error correction rate, allowing the developers more flexibility to choose the most suitable CLC design for their applications. The main drawback of the CLC versions proposed until now is the number of redundant bits, particularly for a 16-bit word, although the authors [16] shown that this drawback may be reduced as the data word applied increases. Furthermore, these same authors also presented a new correction mode named CLC Extended (CLC-E), which increases the error correction capacity of CLC due to the double-checking of the codeword, without adding redundant bits.…”