CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC

Silva, Felipe; Muniz, Adahil; Silveira, Jarbas; Marcon, César

doi:10.1109/sbcci50935.2020.9189901

Cited by 6 publications

(9 citation statements)

References 19 publications

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“…In the table, we can see that most proposals use ECCs with different redundancy. From these, in the ones where no physical reconfiguration is performed ( [41,42,50] and the static version of our proposal), the encoding and decoding circuitry of all ECCs is physically implemented, increasing the hardware overhead.…”

Section: Comparison With Other Proposalsmentioning

confidence: 99%

“…If we analyze the other proposal that keeps the redundancy [42], we realize that actually, only one code is implemented in the alternatives. The only difference between the alternatives is the decoding mode, being possible to opt between a simple and fast (although with fewer correction capability) mode and a higher correction capability mode (but more complex and slow).…”

Section: Comparison With Other Proposalsmentioning

confidence: 99%

“…Analyzing the ECCs used, we utilize in our proposals two simple ECCs, while in most proposals in the table, other more complex ECCs (BCH [42,50], OLSC [47,48] or CLC [42]) are applied. The reason is mainly the fault hypothesis assumed.…”

Section: Comparison With Other Proposalsmentioning

confidence: 99%

“…In Reference [41], Shin et al propose an adaptive ECC with three correction capabilities (1-, 2-and 4-errors) that adapts depending on the error frequency, which is analyzed in the control unit. Similarly, Silva et al present in [42] CLC-adaptive, a column line code-based ECC able to activate CLC-Extended decoder depending on the result of initial CLC-standard decoding.…”

mentioning

confidence: 99%

“…Last but not least, the only proposals that trigger the system adaption by the detection of an intermittent error are our proposals. Others adapt to voltage scaling [41,47], to the overall number of failed cells (counted by the OS) [48], or to a calculated bit error rate stored in an internal table called "reliability map" [50]; finally, in [42] when the CLC-S decoding detects that the number of errors exceeds its error correction capabilities, it launches the second decoding in CLC-E mode.…”

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confidence: 99%

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Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

et al. 2020

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Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

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Section: Comparison With Other Proposalsmentioning

confidence: 99%

Section: Comparison With Other Proposalsmentioning

confidence: 99%

Section: Comparison With Other Proposalsmentioning

confidence: 99%

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confidence: 99%

mentioning

confidence: 99%

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Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

et al. 2020

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A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

Gil-Tomás,

Saiz-Adalid,

Gracia-Morán

et al. 2024

IEEE Access

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MBU is an increasing challenge in SRAM memory, due to the chip's large area of SRAM, and supply power scaling applied to reduce static consumption. Powerful ECCs can cope with random MBUs, but at the expense of complex encoding/decoding circuits, and high memory redundancy. Alternatively, radiation-hardened cell is an alternative technique that can mask single or even double node upsets in the same cell, but at the cost of increasing the overhead of the memory array. The idea of this work is to combine both techniques to take advantage of their respective strengths. To reduce redundancy and encoder/decoder overheads, SEC Hamming ECC has been chosen. About hardened cells, well-known and robust DICE cells, able to tolerate one node upset, have been used. To assess the proposed technique, we have measured the correction capability after a fault injection campaign, as well as the overhead (redundancy, area, power, and delay) of memory and encoding/decoding circuits. Results show high MBU correction coverages with an affordable overhead. For instance, for very harmful 8-bit random MBUs injected in the same memory word, more than 80% of the cases are corrected. Area overhead values of our proposal, measured with respect to double and triple error correction codes, are less than x1.45. To achieve the same correction coverage only with ECCs, redundancy, and overhead would be much higher.

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