Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology

Wei, Zhaopeng; Leduc, Yves; Foucauld, Emeric de; Jacquemod, G.

doi:10.1109/newcas.2017.8010120

Cited by 5 publications

(7 citation statements)

References 4 publications

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“…The next step is to combine the current mirror and the RO to implement a complete VCO, then a PLL. We can notice that the Phase-Frequency Detector, the charge pump, and the divider will be implemented using the complementary logic and the BG control [11].…”

Section: Resultsmentioning

confidence: 99%

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Wei

Jacquemod

Leduc

et al. 2019

Active and Passive Electronic Components

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

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Section: Resultsmentioning

confidence: 99%

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Wei

Jacquemod

Leduc

et al. 2019

Active and Passive Electronic Components

Self Cite

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“…This new complementary inverter will offer two other advantages very important for ring oscillator realization. The first one concerns the duty cycle, which has to be close to 50% and low jitter [3]. Secondly, this topology enables an oscillator with an even number of inverters (cf.…”

Section: Ro Designmentioning

confidence: 99%

“…In the field of CDR architectures, closed-loop systems, such as Phase Locked Loop (PLL) and Delay Locked Loop (DLL), excel in providing low-jitter performance, making them the preferred choice in many applications [1][2][3][4][5][6]. However, open-loop CDR structures offer distinct advantages, particularly in terms of low power consumption, fast locking time, and simplicity of design, often resulting in cost-effective solutions [7].…”

Section: Introductionmentioning

confidence: 99%

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A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

Mao,

Charlon,

Leduc

et al. 2024

JLPEA

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In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2.

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“…In this case, the sampling occurs farthest from the previous and following data transitions, providing a maximum margin for jitter [2]. Indeed, FDSOI 28nm technology allows us to create a complementary inverter by using the back-gate of the transistor to symmetrize its outputs [3]. Complementary inverters allow us to implement back-gate auto-biasing feedback and to realize a QRO with an even number of inverters.…”

Section: Introductionmentioning

confidence: 99%

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Mao

Charlon

Jacquemod

et al. 2022

Preprint

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In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors allows us to create a QRO (Quadrature Ring Oscillator) reducing both size and power consumption. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we can propose a low power ILCDR with low jitter and fast locking time for burst-mode applications. The main novelty consists in the implementation of a complementary QRO based on back-gate control using FDSOI technology in order to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (27 PRBS) at 868Mbps, the recovered clock jitter is 18.5 ps (1.6%UIp-p) and the recovered data jitter is 18.7 ps (1.6%UIp-p). With a 0.6 V power supply, the power consumption is 4.67 mA (2.8 mW). The estimated Chip size is around 6600 µm².

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Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology

Cited by 5 publications

References 4 publications

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

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