Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology

Kar, Gouri Sankar; bosch, G. Van den; Cacciato, A.; Blomme, Pieter; Aerde, S. Van; Arreghini, A.; Breuil, L.; Keersgieter, A. De; Paraschiv, Vasile; Vrancken, C.; Douhard, Bastien; Richard, Olivier; Debusschere, I.; Houdt, J. Van; Tang, B. J.

doi:10.1109/imw.2011.5873209

Cited by 20 publications

(8 citation statements)

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“…The conventional method of generating holes h in the undoped poly‐Si channel in the 3D V‐NAND flash cell is to use the hole h injection from the p + ‐type substrate (the TCAT cell) or to use the GIDL effect (the BiCS cell). [ 102 ] While these two technologies could be available to the 3D configuration, the former can be unfavorable to the 4D V‐NAND flash technology with the PUC scheme, as it can no longer make use of the p + ‐substrate.…”

Section: Device Configuration: 2d Vs 3d V‐nandmentioning

confidence: 99%

Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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Section: Device Configuration: 2d Vs 3d V‐nandmentioning

confidence: 99%

Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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“…We find in case of a network with n x xn y nodes: (4). The surface of the cylindrical poly-Si channel is modeled as a resistive network (right).…”

Section: Resistive Network Modelmentioning

confidence: 99%

Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

Degraeve

Toledano-Luque

Arreghini

et al. 2013

2013 IEEE International Electron Devices Meeting

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The characterization of vertical poly-Si transistors, important for optimizing vertical SONOS memory configurations, is studied by means of a resistive network model. The statistical variation of the I SD -V G characteristics allows to extract the poly-Si grain size and from the sub-threshold regime information on the energy distribution of the poly-Si defects is extracted. This model indicates the separated impact of interface states and poly-Si states on current and V th . Introduction and purpose

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“…Under this trend, charge trapping (CT) flash memory technology has long been investigated and proposed as the most promising candidate within its domain due to its immunity to stress-induced leakage current and reduced coupling capacitance. As such, this technology has thus been recently attracting considerably more attention since it is ideally suitable for three-dimensional (3-D) vertical architectures which exploits the third dimension of the devices to fulfil the ever-increasing demand for bit cost [1][2][3][4][5][6][7][8]. 3-D CT NAND flash is also forecasted to continue the trend of scaling NAND flash below the 15 nm technology node [9].…”

Section: Introductionmentioning

confidence: 99%

A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory

Lun

Zhao

et al. 2016

Sci. China Inf. Sci.

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This work presents a self-consistent two-dimensional (2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data, which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory. Keywords charge trapping memory, semiconductor device modeling, 2-D charge transport, 3-D NAND flash, device modeling and simulation Citation Lun Z Y, Du G, Zhao K, et al. A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory.

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Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology

Cited by 20 publications

References 1 publication

Review of Semiconductor Flash Memory Devices for Material and Process Issues

Review of Semiconductor Flash Memory Devices for Material and Process Issues

Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory

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