Novel approaches to the design of VLSI RNS multipliers

Radhakrishnan, D.; Yuan, Yongqiang

doi:10.1109/82.204109

Cited by 38 publications

(19 citation statements)

References 9 publications

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“…The multiplier outperforms all previous designs in terms of area. However, in terms of time complexity, the designs in [17,61] as well as ROM-based ones outperform the multiplier proposed in [57] for most prime moduli p < 2 7 . Nevertheless, the combined time/area product in [57] is always less than that of other designs.…”

Section: Combinatorial Architecturesmentioning

confidence: 93%

Efficient Hardware Implementation of Finite Fields with Applications to Cryptography

et al. 2006

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The paper presents a survey of most common hardware architectures for finite field arithmetic especially suitable for cryptographic applications. We discuss architectures for three types of finite fields and their special versions popularly used in cryptography: binary fields, prime fields and extension fields. We summarize algorithms and hardware architectures for finite field multiplication, squaring, addition/subtraction, and inversion for each of these fields. Since implementations in hardware can either focus on high-speed or on area-time efficiency, a careful choice of the appropriate set of architectures has to be made depending on the performance requirements and available area.Key words Field arithmetic · cryptography · efficient implementation · binary field arithmetic · prime field arithmetic · extension field arithmetic · Optimal extension fields. (2000) 12-02 · 12E30 · 12E10. Mathematics Subject Classifications

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Section: Combinatorial Architecturesmentioning

confidence: 93%

Efficient Hardware Implementation of Finite Fields with Applications to Cryptography

et al. 2006

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“…For the implementation of the isomorphism, we considered the two alternatives of [17,21], and selected the one with the lower cost for the specific RNS base. Figure 8.3 shows the plots of the ratio between the TCS and RNS values for DSE of the MADD units.…”

Section: Tcs and Rns Maddsmentioning

confidence: 99%

RNS Applications in Digital Signal Processing

Cardarilli

Nannarelli

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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The Residue Number System (RNS) as an alternative to binary representation in digital systems has been studied extensively in the last decades [1,26]. The attractive feature of the RNS is that for operations such as addition and multiplication, a large dynamic range (bit-width) can be divided into sub-ranges of reduced bit-width by splitting the datapath in independent parallel channels where the operations can be executed faster (shorter carry propagation) [26].The main drawback is that converters are required to interface an RNS datapath to the conventional systems based on binary representation, so the use of RNS is justified when the number of operations to be performed in RNS, without conversions, is significant.Over the years, several applications in Digital Signal Processing (DSP), such as digital filters, have benefit from the RNS implementation, e.g., [8,11,15,24].Here, we describe the RNS implementation of a number of DSP algorithms by comparing their performance (clock rate, area, and power dissipation) to the same algorithms implemented in the traditional two's complement number system (TCS), and discussing some trade-offs.In Sect. 8.2, we recall the main RNS concepts to introduce the notation used in the chapter.In Sect. 8.3, we explain the main criteria to choose the RNS base and discuss same trade-offs in choosing the right base for a given application.

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“…If the change of variables (20) is performed in (18), we obtain (19). Hence, a multiplier can be used as a converter if the input assignments defined by (20) are followed.…”

Section: The Multiplier As a Binary-to-residue Convertermentioning

confidence: 99%

“…The first stage of the multiplication operation is described by (18) while the function of a -bit binary-to-residue converter is given by (19) Assume that the partial product sequence is replaced by a bit sequence according to the rule otherwise.…”

Section: The Multiplier As a Binary-to-residue Convertermentioning

confidence: 99%

Multifunction architectures for RNS processors

Paliouras

Stouraitis

1999

IEEE Trans. Circuits Syst. II

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Novel very large-scale integration architectures and a design methodology for adder-based residue number system (RNS) processors are presented in this paper. The new architectures compute residues for more than one modulus either serially or in parallel, while their use can increase the resource utilization in a processor. Complexity is reduced by sharing common intermediate results among the various RNS moduli channels and/or operations that compose an RNS processor. The presented architectures are distinguished into two subtypes, depending on whether the inter-channel parallelism is preserved or not. The multifunction architecture paradigm is demonstrated by its application in residue multiplication, binary-to-residue conversion, quadratic RNS (QRNS) mapping, and base extension. The derived architectures are compared to previously reported equivalent ones and are found to be efficient in area 2 time product sense. Finally, the proposed design methodology reveals a new tradeoff in residue processor design, leading to more efficient RNS processors.Index Terms-Design methodology, digital signal processing, residue arithmetic.

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Novel approaches to the design of VLSI RNS multipliers

Cited by 38 publications

References 9 publications

Efficient Hardware Implementation of Finite Fields with Applications to Cryptography

Efficient Hardware Implementation of Finite Fields with Applications to Cryptography

RNS Applications in Digital Signal Processing

Multifunction architectures for RNS processors

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