Notary: Hardware techniques to enhance signatures

Yen, Luke; Draper, Stark C.; Hill, Mark D.

doi:10.1109/micro.2008.4771794

Cited by 41 publications

(48 citation statements)

References 57 publications

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“…Bit extraction selects a predefined bit-field (address key) from a block address as a signature index (hash value). To spread the frequently occurring patterns over all indexes, more efficient hash functions such as bit-permutation hashing [6], XOR-based hashing [24], or H3 hashing [19,22] can be used. Each hash function sets one signature bit per address.…”

Section: A Backgroundmentioning

confidence: 99%

“…There are lots of applications using hardware signatures in computer design [22,24]. In this subsection, we focus on the previous work with signatures for conflict detection in TM systems.…”

Section: B Related Workmentioning

confidence: 99%

“…Recently, several signature schemes have been proposed to design area-efficient signatures or to improve TM performance [19,22,24,25]. Sanchez et al [22] suggest a parallel Bloom filter.…”

Section: B Related Workmentioning

confidence: 99%

“…Several signature designs have been proposed to enhance area-efficiency or to improve TM performance [19,22,24,25]. In all these schemes, false positives are assumed to be detrimental to performance, so they attempt to reduce the total number of false positives.…”

Section: Introductionmentioning

confidence: 99%

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Locality-aware adaptive grain signatures for Transactional Memories

Choi

Draper

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing (IPDPS)

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Abstract-Transactional Memory (TM) has attracted considerable attention because it promises to increase programmer productivity by making it easier to write correct parallel programs. To maintain correctness in the face of concurrency, detecting conflicts among simultaneously running transactions is an essential element. Hardware signatures have been proposed as an area-efficient mechanism for conflict detection. A signature can summarize an unbounded amount of addresses and misses no conflicts, but could falsely declare conflicts even when no true conflict exists (false positives) due to aliasing and occupancy. Previous signature designs assume that false positives are destructive to performance and attempt to reduce the total number of false positives.In this paper, we show that some false positives can be helpful to performance by triggering the early abortion of a transaction which would encounter a true conflict later anyway. Based on this observation, we propose an adaptive grain signature to improve performance by dynamically changing the range of address keys based on the history. With the use of adaptive grain signatures, we can increase the number of performance-friendly false positives as well as decrease the number of performance-destructive false positives.

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Section: A Backgroundmentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

“…Recently, several signature schemes have been proposed to design area-efficient signatures or to improve TM performance [19,22,24,25]. Sanchez et al [22] suggest a parallel Bloom filter.…”

Section: B Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Locality-aware adaptive grain signatures for Transactional Memories

Choi

Draper

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing (IPDPS)

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“…Yen, et al, describes the idea of using entropy to represent the randomness of instruction addresses [18]. According to Equation 1, in the case of memory entropy, variable x represents the memory addresses that appear in the program execution.…”

Section: B Memorymentioning

confidence: 99%

ISA-independent workload characterization and its implications for specialized architectures

Shao

Brooks

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Specialized architectures will become increasingly important as the computing industry demands more energyefficient designs. The application-centric design style for these architectures is heavily dependent on workload characterization of intrinsic program characteristics, but at the same time these architectures are likely to be decoupled from legacy ISAs. In this work, we perform ISA-independent workload characterization for a variety of important intrinsic program characteristics relating to computation, memory, and control flow. The analysis is performed using a JIT compiler that emits ISA-independent instructions. We compare this analysis with an x86 trace and find that several of the analyses are highly sensitive to the ISA. We conclude that designers of specialized architectures must adopt ISA-independent workload characterization approaches.

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