Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

Chang, Dong Jin; Kim, Wan; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung‐Tak

doi:10.1109/tcsi.2016.2612692

Cited by 17 publications

(6 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…12. Since each calibrated weight of the coarse ramp is the accumulation of the resistor weights, the quantization error in each resistor weight will slightly degrade the linearity of the coarse ramp [31]. For the dynamic performance, after the foreground calibration, the standard deviation (std) and average (mean) of ENOB are improved from 0.09/4.83 bits to 0.33/10.85 bits and the standard deviation and average of SFDR are improved from 2.71/39.92 dB to 4.09/72.03 dB.…”

Section: A Behavior Simulationmentioning

confidence: 99%

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

Zhang

Ning

et al. 2020

IEEE Access

View full text Add to dashboard Cite

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-todigital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm 2 and the power consumption is 72 μW. INDEX TERMS Column-parallel ADC; single-slope (SS) ADC; two-step ADC; foreground calibration

show abstract

Section: A Behavior Simulationmentioning

confidence: 99%

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

Zhang

Ning

et al. 2020

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Without errors, sum of in-phase and anti-phase sampled data becomes equal to

D_{\max c o d e} (i)

. The ADC has an average power of quantization noise V LSB 2 /12 and the magnitude of acceptable error is smaller than 0.5 LSB [23]. Then, if

e_{i n s t a n t}

is larger than 0.5 LSB, the erroneous sample can be corrected with its counterpart interpolated value that is estimated from its adjacent anti-phase samples.…”

Section: Display-based Multi-sensor Interfacementioning

confidence: 99%

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

Park

Kim

Eom

et al. 2017

Sensors

View full text Add to dashboard Cite

This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

show abstract

“…As a result the DAC linearity may be much worse than the target precision. Ideally before instrumentation the system should perform a calibration procedure that determines the actual capacitor weights W D AC and recovers any lost accuracy due to mismatch in the digital domain [25], [26]. Digital calibration techniques are extensively used for SAR converters because they enable more aggressive capacitor sizing without introducing extra analogue complexity that does not benefit from technology scaling [27].…”

Section: Foreground Calibration For the Sarmentioning

confidence: 99%

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

Leene

Constandinou

2017

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

The instrumentation systems for implantable brainmachine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0-2 MASH topology. This configuration uses a specialized FIR window to decimate the modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using 0.18 μm CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm 2 silicon footprint. Moreover, a 14 fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications. Index Terms-A/D conversion, bio-sensors arrays, oversampling, incremental delta-sigma, FIR decimation, low power analogue, ADC calibration. I. INTRODUCTION T HE emergent market for wearable electronics and implantable devices for personalized health care has resulted in a growing demand for miniaturized battery powered systems that wirelessly connect a network of sensors [1]. These systems rely extensively on high precision analogue to digital conversion to leverage digital processing techniques and accommodate stringent diagnostic requirements [2]. As a result the ADC power, area, and precision can have a profound impact on a system's overall capabilities. For this reason oversampling techniques using ADCs have already been used extensively to accommodate the niche characteristics of biomedical devices and acquire low frequency bio-signals [3]. More recent developments allow these techniques to be more applicable to large sensor arrays using an incremental analogue to digital converter (IADC) topology [4]. This is in contrast to the conventional use where a single oversampling ADC continuously converts the signal from a single sensing unit with exceptional efficiency. IADC designs are unique in Manuscript

show abstract

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

Cited by 17 publications

References 14 publications

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

Contact Info

Product

Resources

About