Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture

Abstract

We propose and computationally analyze a nonvolatile static random access memory (NV-SRAM) cell using magnetic tunnel junctions (MTJs) with magnetic-field-free current-induced magnetization switching (CIMS) architecture. A pair of MTJs connected to the storage nodes of a standard SRAM cell with CIMS architecture enables fully electrical store and restore operations for nonvolatile logic information. A wide range of tunneling magnetoresistance (TMR) ratios and V half (the bias voltage when the TMR ratio is reduced to half its original value) values are acceptable for the operation of the proposed NV-SRAM cell. Successful operation can be easily achieved when moderate TMR and V half values such as 100% and 100 mV, respectively, are used. The proposed NV-SRAM is expected to be a key component of next-generation power-gating logic systems with extremely low static-power dissipation. #

Devices and Applications: Spin Transistors and Spin Logic Devices

“…Design of PS-MOSFETs can be easily achieved using a general circuit simulator such as SPICE with an appropriate circuit model of MTJs [85]. Therefore, spin transistors can be employed in logic circuits sooner rather than later, when the MRAM technology is added on the CMOS logic platform.…”

“…Thus, nonvolatile memory circuits, such as nonvolatile registers, register files, and caches, have a great impact on highly efficient PG of logic systems. Recently, NVPG has been proposed, in which NV-SRAM and NV-DFF cells based on the PS-MOSFET architecture were employed for these nonvolatile memory circuits [1,85,[97][98][99][100]. The NV-SRAM-and NV-DFF-based circuits are highly suitable for NVPG owing to their important features of "electrical separation of the normal SRAM/FF operation and the nonvolatile memory operation."…”

“…This architecture allows temporally and spatially optimized granularity of power gating with high energy efficiency that cannot be achieved only by the present CMOS technology. Figure 18 schematically shows a proposed NVPG multicore processor (NVPG-MP) [97,99,100]. (In this example, first-level and second-level caches (L1$s and L2$) are employed.…”

“…19b, since only a part of data locally stored in the lower-level caches is required for quick restart of the system. Therefore, the partially nonvolatilized lower-level caches are preferable [97,99,100]. The nonvolatile main memory using a large-capacity high-speed nonvolatile memory such as ReRAM, spin-RAM, and PRAM has an advantage in instant-on rebooting.…”

Static Noise Margin and Power-Gating Efficiency of a New Nonvolatile SRAM Cell Based on Pseudo-Spin-Transistor Architecture

“…Nonvolatile caches and registers have a great impact on highly efficient PG so-called nonvolatile PG (NV-PG) [1,2]. Recently, we proposed NV-SRAM cell [3][4][5] and flip-flop (NV-FF) [2,[6][7][8] based on pseudo-spin-transistor architecture. These are suitable for NV-PG logic systems.…”