Static Noise Margin and Power-Gating Efficiency of a New Nonvolatile SRAM Cell Based on Pseudo-Spin-Transistor Architecture

Abstract

Static noise margin (SNM) and power-gating efficiency were computationally analyzed for our proposed nonvolatile SRAM (NV-SRAM) cell based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque MTJs (STT-MTJs). The NV-SRAM cell has the same SNM as an optimized 6T-SRAM cell. SNM was also evaluated for other recently-proposed NV-SRAM cells using STT-MTJs, and we showed that their SNMs were deteriorated owing to the effect of the constituent STT-MTJs. Break-even time (BET) and power efficiency were analyzed for the NV-SRAM cell using PSMOSFETs. The BET can be successfully minimized by controlling the bias of the cell. The average power dissipation can be effectively reduced by power-gating (PG) executions, and the further reduction is made possible by introducing a sleep mode (which is a data retention mode using a low power supply voltage). Keywords-component; power-gating; nonvolatile SRAM; STT-MTJ; break-even time; static noise margin I. INTRODUCTION PG is the most attractive architecture to reduce static power dissipation in advanced CMOS logic systems, such as microprocessors and SoCs. Nonvolatile caches and registers have a great impact on highly efficient PG so-called nonvolatile PG (NV-PG) [1,2]. Recently, we proposed NV-SRAM cell [3-5] and flip-flop (NV-FF) [2,6-8] based on pseudo-spin-transistor architecture. These are suitable for NV-PG logic systems. The NV-SRAM cell [3] is configured with a standard 6T-SRAM cell and PS-MOSFETs that consist of an STT-MTJ and an ordinary MOSFET [3]. For the stable operations of the cell, sufficient SNMs for the SRAM operations are required as well as ordinary 6T-SRAM cells.However, SNMs have not been systematically analyzed for our proposed and other currently-proposed NV-SRAM cells using STT-MTJs. BET is also an important index for the PG application of the NV-SRAM cells, which determines a minimum shutdown period of PG. For our proposed cell, the BET is mainly governed by the write operation to the STTMTJs owing to the relatively high write current (I MTJ ) for current-induced magnetization switching (CIMS) of the STTMTJs. Static leakage currents in the cell also affects the BET. For the NV-FF based on the PS-MOSFET architecture, the BET can be reduced by optimizing the size of its constituent transistors [8]. On the other hand, this technique is not suitable for the NV-SRAM cell owing to the restriction in its cell design

Devices and Applications: Spin Transistors and Spin Logic Devices

“…Although PG systems have already been developed with these techniques, disadvantages exist depending on architecture used to achieve PG, e.g., limited static-power reduction, addition of purpose-built interconnects for data transfer, extra time and power for data transfer using a bus line, excess area occupation for backup devices, and greater layout/control complexity due to the dualpower rails. These disadvantages would be solved by introducing nonvolatile SRAM (NV-SRAM) and nonvolatile FF (NV-FF) into PG systems [18,[92][93][94][95][96][97][98].…”

“…Nevertheless, the MTJs connected to the NV-SRAM/NV-FF cell will deteriorate their circuit performance, such as degrading the operating speed, variability tolerance, and static noise margin (SNM) and also increasing the power dissipation during normal SRAM/FF operation mode. In order to overcome these problems, a new approach using spin-functional MOSFETs has been proposed [18,[92][93][94][95][96][97][98]. Since the spin-functional MOSFETs can electrically separate the bistable circuit from the nonvolatile memory elements, they have little or no deleterious effects on the bistable circuit operation, as shown below.…”

“…Since the spin-functional MOSFETs can electrically separate the bistable circuit from the nonvolatile memory elements, they have little or no deleterious effects on the bistable circuit operation, as shown below. Figure 12a shows the circuit configuration of an NV-SRAM cell, in which two PS-MOSFETs are connected to the storage nodes of a standard SRAM cell [18,[92][93][94]. Figure 13 shows simulated waveforms for the cell operations.…”

“…Figure 14 shows SNM for the read operation of various NV-SRAM cells. Note that the ordinary SRAM part of all the NV-SRAM cells was designed by reference to an optimized 6T-SRAM cell using 65 nm MOSFETs [93,94]. For all the cells, the read operation gives the worst-case SNM.…”

“…BET SR can be successfully reduced by write bias control (for the SR and CTRL lines shown in Fig. 12) and cell design optimization (channel width/length (W PSM /L PSM ) of the PS-MOSFETs) for the NV-SRAM and NV-DFF optimization, respectively [92][93][94][95][96][97]. BET SR can also be reduced by shortening the write pulse width (t wpw ) for the MTJs [92,97].…”