Nonvolatile Semiconductor Memory Technology

Brown, W.D.; Brewer, J.E.

doi:10.1109/9780470545409

Cited by 103 publications

(48 citation statements)

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“…(iv) For the CMOS relay cell area, we have used an estimate of 5F 2 CMOS , resulting in β = √ 5/2 ≈ 1.6. We believe this is a fair estimate for the cells shown in figure 3(a) implemented in a style similar to the usual NAND flash memory cell [31,38]. If this estimate seems too optimistic, note that it does not affect the results in the most realistic case (n + a) > R 2 ; see equation (23 …”

Section: Chip Area Assumptionsmentioning

confidence: 96%

“…With this assumption, the read and write operations are very similar to those in semiconductor memories [14], especially floating-gate nonvolatile memories (NVM [31]). For READ operation, one of the relay cells (e.g., cell 1 in figure 2(a)) applies voltage V READ /2 to the corresponding word nanowire, while the complementary relay cell (cell 2 in figure 2(a)) connects the selected device, via the bit nanowire, to the CMOS data line biased by voltage −V READ /2, and then to the input of a CMOS sense amplifier.…”

Section: Memory Structurementioning

confidence: 99%

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Prospects for terabit-scale nanoelectronic memories

2004

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We have calculated the minimum chip area overhead, and hence the bit density reduction, that may be achieved by memory array reconfiguration (bad bit exclusion), combined with error correction code techniques, in prospective terabit-scale hybrid semiconductor/nanodevice memories, as a function of the nanodevice fabrication yield and the micro-to-nano pitch ratio. The results show that by using the best (but hardly practicable) reconfiguration and block size optimization, hybrid memories with a pitch ratio of 10 may overcome purely semiconductor memories in useful bit density if the fraction of bad nanodevices is below ∼15%, while in order to get an order-of-magnitude advantage in density, the number of bad devices has to be decreased to ∼2%. For the simple 'Repair Most' technique of bad bit exclusion, complemented with the Hamming-code error correction, these numbers are close to 2% and 0.1%, respectively. When applied to purely semiconductor memories, the same technique allows us to reduce the chip area 'swelling' to just 40% at as many as 0.1% of bad devices. We have also estimated the power and speed of the hybrid memories and have found that, at a reasonable choice of nanodevice resistance, both the additional power and speed loss due to the nanodevice subsystem may be negligible.

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Section: Chip Area Assumptionsmentioning

confidence: 96%

Section: Memory Structurementioning

confidence: 99%

Prospects for terabit-scale nanoelectronic memories

2004

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“…Then, using a proprietary laser scanning setup [16], areas sensitive to the ionisation with laser radiation (bright areas) were found ( Figure 7). A standard Flash memory array consists of the current source, memory cells, row and column selectors and a sense amplifier consisting of an amplifier and a comparator to the reference cell signal which will distinguish between 0 and 1 [8]. Obviously, if we are interested in restoring the state of previously erased or discharged cell we have to either reduce the current flowing through the cell, or increase the reference voltage of the read sense amplifier, or reduce the coefficient of the amplification itself.…”

Section: Semi-invasive Resultsmentioning

confidence: 99%

“…There are also memory devices with a fully analog design, which store charges proportional to the input voltage [7]. There are two basic processes that allow placing electrons on the floating gate -Fowler-Nordheim tunnelling and channel hot electron (CHE) injection [8]. Both processes are destructive to the very thin dielectric insulation layer between the floating gate and the channel of a transistor.…”

Section: Introductionmentioning

confidence: 99%

Data Remanence in Flash Memory Devices

Skorobogatov

2005

Cryptographic Hardware and Embedded Systems – CHES 2005

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Abstract. Data remanence is the residual physical representation of data that has been erased or overwritten. In non-volatile programmable devices, such as UV EPROM, EEPROM or Flash, bits are stored as charge in the floating gate of a transistor. After each erase operation, some of this charge remains. Security protection in microcontrollers and smartcards with EEPROM/Flash memories is based on the assumption that information from the memory disappears completely after erasing. While microcontroller manufacturers successfully hardened already their designs against a range of attacks, they still have a common problem with data remanence in floating-gate transistors. Even after an erase operation, the transistor does not return fully to its initial state, thereby allowing the attacker to distinguish between previously programmed and not programmed transistors, and thus restore information from erased memory. The research in this direction is summarised here and it is shown how much information can be extracted from some microcontrollers after their memory has been 'erased'.

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“…1 [3]: the gate F of an NMOS (N-channel Metal-Oxide-Semiconductor) transistor (drain D, source S) is kept floating by electrical isolation. The conduction of the channel is modulated by the potential applied on a control gate C, capacitively coupled to F, and depends on the floating gate total charge Q F .…”

Section: Introductionmentioning

confidence: 99%