Nonvolatile Memory Effects of NiO Layers Embedded in Al[sub 2]O[sub 3] High-k Dielectrics Using Atomic Layer Deposition

Cho, Wontae; Lee, Su Yeon; Chung, Taek‐Mo; Kim, Chang Gyoun; An, Ki‐Seok; Ahn, Jae‐Pyoung; Lee, Jun-Young; Lee, Jun Young; Hwang, Jin‐Ha

doi:10.1149/1.3380827

Cited by 12 publications

(12 citation statements)

References 13 publications

(9 reference statements)

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“…Recently, oxide semiconductor of ZnO [26][27][28][29] and NiO [30] have found their new applications as CTL. The main reason that makes ZnO as a desirable CTL in Si-channel based memory is the unique property of a negative conduction band offset (NCBO) with respect to Si which provides several advantages for memory operation including (1) higher program speed because of the larger tunneling current from Si substrate that causes a larger amount of electron injection.…”

Section: Trapping Layermentioning

confidence: 99%

“…On the other hand, owing to the large number of localization sites that are helpful to obtaining a large memory window, NiO is also a promising candidate for CTL for charge storage. Employing oxide semiconductor as the CTL is a new field in the flash memory research [26][27][28][29][30], however, its memory performance still needs to be improved since the operation voltage remains larger than 10 V. In addition to the aforementioned properties for ZnO and NiO, they correspond to n-type and p-type semiconductor respectively. By integrating these unique material characteristics, C. E. Sun et al first explored a stacked ZnO/NiO that possesses n/p diode properties as the CTL for flash memory [31].…”

Section: Trapping Layermentioning

confidence: 99%

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Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Chen

Teng

Chang

et al. 2016

IEEE J. Electron Devices Soc.

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Journal of the Electron Devices Society 6 V. CONCLUSION With incumbent flash memory devices operated in the range of 15-17 V, it is imperative to pursue green flash memory that can be operated at voltage less than 10 V to realize a sustainable environment. In this paper, two promising CTL types based on crystalline oxide including crystalline high-k dielectric and crystalline oxide semiconductor which possess the capability to achieve this goal are reviewed. For CTL based on crystalline high-k dielectric, the distinct advantage for memory operation is the k value higher than 30 which is much higher than the amorphous counterpart and beneficial to reduce operation voltage since a higher effective electric field can be exerted on the tunnel SiO2 due to electric flux density continuity. The most concerned retention issue of adopting a crystalline high-k CTL has also be circumvented by passivation of grain boundaries related defects through plasma treatment. The concept of employing crystalline high-k dielectric as CTL not only works for Si-channel flash memory but also Ge-channel memory devices which enable superior memory performance to Si-based counterpart due to higher carrier mobility and more desirable band structure. For CTL based on crystalline oxide semiconductor, a CTL formed by stacking n-type and p-type oxide semiconductor demonstrates typical diode characteristics with a built-in internal electric field. It is the unique internal field that enhances P/E speed while reducing the operation voltage. Both kinds of CTL create a differentiating and pioneering technology that gains an outlook on realizing green flash memory devices.

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Section: Trapping Layermentioning

confidence: 99%

Section: Trapping Layermentioning

confidence: 99%

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Chen

Teng

Chang

et al. 2016

IEEE J. Electron Devices Soc.

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“…Our recent work reported the effect of tunneling and charge trapping layers on the nonvolatile memory effects in terms of quantitative approach for evaluating charge-trapping phenomena. 25 The atomic layer deposition of NiO did not suffer from the detrimental effect of C and N present in the initial precursors, since the ALD-prepared NiO thin films exhibited resistive switching 26 and p-type thermoelectric features. Although sputtering can be used for deposition of antiferroelectric NiO thin films, atomic layer deposition can be recognized as one of the practical approaches, due to superior conformal coverage and high-precision layer-based control in thickness.…”

mentioning

confidence: 99%

“…In the Si/Al 2 O 3 /NiO/Al 2 O 3 nanolaminates, the maximized memory window of 13.8 eV was measured from Al 2 O 3 (3 nm)/NiO(5 nm)/Al 2 O 3 (20 nm). 25 If the tunneling layer is too thin, the memory retention can be degraded due to less effectiveness in barriers formed between the tunneling layer and semiconducting Si. If the thickness is too thick, there can be some difficulty in overcoming the energy barriers, leading to high electric field and ultimately, the spurious increase in operation conditions.…”

mentioning

confidence: 99%

“…ALD was employed to continuously deposit insulating and charge-trapping layers without any process interruptions. 25 A semiconducting oxide, such as nickel oxide (NiO), has been proposed as a candidate for charge-trapping layers since NiO thin layers have inherent atomic defects in metal vacancies. Our recent work reported the effect of tunneling and charge trapping layers on the nonvolatile memory effects in terms of quantitative approach for evaluating charge-trapping phenomena.…”

mentioning

confidence: 99%

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Comparison of Nonvolatile Memory Effects in Ni-Based Layered and Dotted Nanostructures Prepared through Atomic Layer Deposition

Lee

Kim

Hwang

et al. 2011

Electrochem. Solid-State Lett.

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Nano-floating gate memory devices were fabricated by using nickel nanocrystals as a charge-trapping portion embedded into Al 2 O 3 thin films. Ni nanocrystals were prepared via a thermal reduction of nanoscale NiO layers deposited by atomic layer deposition. Although the continuous deposition of insulating Al 2 O 3 and semiconducting NiO thin films allowed the facile fabrication of charge-trap, the corresponding retention feature suffers from inferior charge trapping/detrapping. On the other hand, the Ni nanocrystals enhanced the retention behavior and exhibited the largest memory window of 13.8 V with the stored charge density of 2.5 Â 10 13 traps/cm 2 , probably due to the isolated formation of charge-trapping centers.Next-generation non-volatile memories will have to meet stringent device performance requirements, such as higher speed, enhanced data storage density, limited device space, and lower power consumption, in addition to possessing nonvolatile features in data storage mode. In particular, nano-floating gate memories (NFGMs) are the dominant type of memory compared to their current competitors, such as phase-change random access memories (RAMs), resistive RAMs, polymer RAMs, magnetic RAMs etc. 1-7 NFGM performance far exceeds the currently-evolved flash memories and dynamic random access memories in terms of operation voltage, consumption power, and data volatility. Further, NFGMs can be effectively adapted to the pre-existing Si processing/technology through the incorporation of sophisticated thin dielectric layers. The performance of NFGMs depends largely upon the delicate function of the charge-trapping materials embedded into the high-k thin films. Furthermore, NFGMs should meet stringent requirements of nonvolatile memories: fast programming/erasing speed, high-number programming/easing cycles, and long-period charge retention.A typical strategy is to combine high-k dielectric materials (Al 2 O 3 , ZrO 2 , HfO 2 , etc. 8-22 ) with metallic and semiconducting nanocrystals such as Pt, Au, Co, Ge, Ni, and silicides. In particular, Ni-based nanocrystals were attempted in the combined form of physical deposition and post thermal treatments. 18-23 The formation of charge-trapping nanocrystals has been shown through physical and chemical deposition of metallic or semiconducting layers followed by thermal or optical annealing or chemical dispersion of nanocrystals onto the dielectric thin films. Those approaches suffer from the disadvantage that processing is discontinuous, while facile continuous processing would be preferred.Since the introduction of atomic layer deposition (ALD) by Suntola, 24 ALD has been gaining widespread attention in semiconductors and flat-panel displays, owing to conformal coverage in lowdimensional structures, superior control in film thickness and robust dielectrics. ALD was employed to continuously deposit insulating and charge-trapping layers without any process interruptions. 25 A semiconducting oxide, such as nickel oxide (NiO), has been proposed as a candidate for charge-...

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Nanolaminates

Szeghalmi¹,

Knez²

2011

Atomic Layer Deposition of Nanostructured Materials

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Nonvolatile Memory Effects of NiO Layers Embedded in Al[sub 2]O[sub 3] High-k Dielectrics Using Atomic Layer Deposition

Cited by 12 publications

References 13 publications

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Toward Low-Power Flash Memory: Prospect of Adopting Crystalline Oxide as Charge Trapping Layer

Comparison of Nonvolatile Memory Effects in Ni-Based Layered and Dotted Nanostructures Prepared through Atomic Layer Deposition

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