Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver

Ben-Romdhane, Manel; Rebai, Chiheb; Ghazel, Adel; Desgreys, Patricia; Loumeau, Patrick

doi:10.1109/tcsii.2011.2172527

Cited by 12 publications

(15 citation statements)

References 13 publications

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“…Starting from E-GSM, UMTS and IEEE802.11a standards specifications, a hybrid homodyne/low-IF architecture design was proposed in [8] for the front-end of the SDR receiver. The input signals are selected by an RF filter.…”

Section: A Mixed Baseband Stagementioning

confidence: 99%

Phase mismatch study and correction of a parallel FBD ΣΔ ADC for SDR receiver

Lahouli¹,

Ben-Romdhane²,

Rebai³

et al. 2015

2015 IEEE International Wireless Symposium (IWS 2015)

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This paper presents the study of phase mismatch in parallel frequency band decomposition (FBD)-based analogto-digital converter (ADC). This architecture is designed for analog-to-digital conversion of wireless communication signals in a software defined radio (SDR) receiver. It is composed of 6 parallel branches based on discrete-time (DT) Σ∆ modulators using single-bit quantizers. The parallel branches operate on different sub-bandwidths and only needed branches are activated according to the selected standard. The division of the signal channel bandwidth on different sub-bandwidths and the digitization of each sub-bandwidth by one of the parallel branches lead to phase mismatching at the frequency boundaries between the adjacent branches. This paper focuses on the phase mismatch study and its correction in the FBD Σ∆-based ADC architecture.Keywords-Sigma delta modulators, frequency band decomposition architecture, software defined radio receiver, phase mismatch.

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Section: A Mixed Baseband Stagementioning

confidence: 99%

Phase mismatch study and correction of a parallel FBD ΣΔ ADC for SDR receiver

Lahouli¹,

Ben-Romdhane²,

Rebai³

et al. 2015

2015 IEEE International Wireless Symposium (IWS 2015)

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“…Table I summarized the channel bandwidth and spacing (Ch BW and Ch sp , respectively), the signal-to-noise ratio SNR at the receiver input (SNR in ) and output (SNR out ), the analog gain relative to a 13 dBm ADC full-scale input, the receiver dynamic range DR in and ADC dynamic range DR ADC from which the ADC resolution Res ADC is deduced. The SDR receiver architecture is a hybrid homodyne/low-IF as proposed for multistandard receiver front-end in [12,13]. The received signals, centered around the frequency f RF , are filtered by an RF filter and amplified with maintaining a low noise.…”

Section: A Baseband Sdr Receiver Specificationsmentioning

confidence: 99%

“…However, E-GSM signals are down-converted to a 100 kHz intermediate frequency to overcome the flicker noise disturbance. Therefore, the E-GSM channel bandwidth is considered equal to 200 kHz [12]. …”

Section: A Baseband Sdr Receiver Specificationsmentioning

confidence: 99%

“…In conventional mixed analog/digital baseband architecture, the downconversion mixer, controlled by the local oscillator (LO), is followed by an AAF, an AGC circuit, then an ADC and finally a channel selection stage [12]. In this paper, the conventional baseband design shown in Fig.…”

Section: A Mixed Baseband Architecturementioning

confidence: 99%

“…The mixed baseband stage is composed of a single 6 th order non-programmable AAF that filters only E-GSM blockers that are outside the IEEE802.11a bandwidth. In this case, there is no need to AGC block use before the ADC [12,13]. The baseband block diagram with Σ∆ FBD based ADC is presented in Fig.…”

Section: A Mixed Baseband Architecturementioning

confidence: 99%

See 2 more Smart Citations

Towards flexible parallel sigma delta modulator for software defined radio receiver

Lahouli

Ben-Romdhane

Rebai

et al. 2014

2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings

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A novel frequency band decomposition architecture based on a single-bit 4 th order sigma delta modulators and intended for a software defined radio receiver is presented in this paper. The parallel designed architecture is flexible with parallel programmable branches. Synthesis results prove that this architecture satisfies the multistandard receiver specifications without the use of automatic gain control circuit. Nevertheless, system level analysis of the mixed baseband architecture using a single passive anti-aliasing filter has revealed adjacent branch interference problems. A design specification for a non-unitary signal transfer function for sigma delta modulators is proposed to cover interferences of adjacent branches.

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Design of a high‐gain silicon BJT and an E‐pHEMT hybrid matrix amplifier with an optimum filter‐matching technique

Sangaran¹,

Kumar²,

Paoloni

2019

IET Microwaves, Antennas & Propagation

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Software Defined Radio (SDR) is an advanced wireless transmission paradigm that permits to support all the consumer wireless protocols such as 2G, 3G, LTE, Wi-Fi (2.4 GHz and 5GHz), Bluetooth and Zigbee, by software rather than hardware. A typical frequency band of operation is in the range 0.5-6 GHz. The challenge to bring a SDR system on portable devices is the availability of Ultra-wide band compact amplifiers with high gain over a wide frequency band. A novel hybrid Silicon BJT and E-pHEMT matrix amplifier with two rows and four columns (2 by 4) of transistors is designed realized and tested demonstrating 0.65-5.8 GHz frequency band to satisfy the SDR specifications. The novel optimum filter matching technique is applied to optimize the performance and overcome the limit of the hybrid approach. The proposed matrix amplifier exhibits an average gain of 37.5dB and average output power of 18dBm across 0.65GHz-5.8GHz band with only 3V supply voltage. The gain is the highest in the state of the art for the frequency range. A bandwidth of 5.15 GHz, 20.3dBm one dB compression point at 1.35GHz, 10% to 16% power added efficiency and 1.2W DC power consumptions are obtained.

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Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver

Cited by 12 publications

References 13 publications

Phase mismatch study and correction of a parallel FBD ΣΔ ADC for SDR receiver

Phase mismatch study and correction of a parallel FBD ΣΔ ADC for SDR receiver

Towards flexible parallel sigma delta modulator for software defined radio receiver

Design of a high‐gain silicon BJT and an E‐pHEMT hybrid matrix amplifier with an optimum filter‐matching technique

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Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver

Cited by 12 publications

References 13 publications

Phase mismatch study and correction of a parallel FBD &#x03A3;&#x0394; ADC for SDR receiver

Phase mismatch study and correction of a parallel FBD &#x03A3;&#x0394; ADC for SDR receiver

Towards flexible parallel sigma delta modulator for software defined radio receiver

Design of a high‐gain silicon BJT and an E‐pHEMT hybrid matrix amplifier with an optimum filter‐matching technique

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Phase mismatch study and correction of a parallel FBD ΣΔ ADC for SDR receiver

Phase mismatch study and correction of a parallel FBD ΣΔ ADC for SDR receiver