Noninvasive leakage power tomography of integrated circuits by compressive sensing

Shamsi, Davood; Boufounos, Petros T.; Koushanfar, Farinaz

doi:10.1145/1393921.1394011

Cited by 19 publications

(13 citation statements)

References 23 publications

(28 reference statements)

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“…The first one employs direct wafer microscopic measurements [Friedberg et al 2005]. The other set of techniques use nondestructive indirect power and delay measurements and sophisticated techniques for solving systems of overconstrainted system of linear equation in presence of noisy data [Alkabani et al 2008a;Shamsi et al 2008].…”

Section: Related Workmentioning

confidence: 99%

Techniques for Design and Implementation of Secure Reconfigurable PUFs

Majzoobi

Koushanfar

Potkonjak

2009

ACM Trans. Reconfigurable Technol. Syst.

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176

127

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Physically unclonable functions (PUFs) provide a basis for many security and digital rights management protocols. PUF-based security approaches have numerous comparative strengths with respect to traditional cryptography-based techniques, including resilience against physical and side channel attacks and suitability for lightweight protocols. However, classical delay-based PUF structures have a number of drawbacks including susceptibility to guessing, reverse engineering, and emulation attacks, as well as sensitivity to operational and environmental variations.To address these limitations, we have developed a new set of techniques for FPGA-based PUF design and implementation. We demonstrate how reconfigurability can be exploited to eliminate the stated PUF limitations. We also show how FPGA-based PUFs can be used for privacy protection. Furthermore, reconfigurability enables the introduction of new techniques for PUF testing. The effectiveness of all the proposed techniques is validated using extensive implementations, simulations, and statistical analysis.

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Section: Related Workmentioning

confidence: 99%

Techniques for Design and Implementation of Secure Reconfigurable PUFs

Majzoobi

Koushanfar

Potkonjak

2009

ACM Trans. Reconfigurable Technol. Syst.

Self Cite

176

127

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“…Calibration is done by transforming and comparing the test IC currents to those produced by Trojanfree simulation models. Gate-level estimation as a method for post-silicon IC characterization has been introduced earlier [2,3,13,9]. Potkonjak et al combined the gate-level estimation with constraint manipulation to detect Trojans using delay and leakage side channels [9].…”

Section: Related Workmentioning

confidence: 99%

Consistency-based characterization for IC Trojan detection

Alkabani

Koushanfar

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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A Trojan attack maliciously modifies, alters, or embeds unplanned components inside the exploited chips. Given the original chip specifications, and process and simulation models, the goal of Trojan detection is to identify the malicious components. This paper introduces a new Trojan detection method based on nonintrusive external IC quiescent current measurements. We define a new metric called consistency. Based on the consistency metric and properties of the objective function, we present a robust estimation method that estimates the gate properties while simultaneously detecting the Trojans. Experimental evaluations on standard benchmark designs show the validity of the metric, and demonstrate the effectiveness of the new Trojan detection.

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“…Li and Lach propose adding on chip delay test structures for Trojan detection [27]. Gate-level characterization was used for postsilicon profiling [28]- [30] and its use for IC Trojan detection was first proposed in [9], [31] and also used in [10]- [13], [32], [33]. However, optimality guarantees (bounds), calibration, sensitivity, and multimodal combining were not discussed in the literature.…”

Section: Related Workmentioning

confidence: 99%