Non-uniform current flow through thin oxide after Fowler-Nordheim current stress

Yamada, Shigeru; Amemiya, Kenta; Yamane, Takeshi; Hazama, H.; Hashimoto, Kouichi

doi:10.1109/relphy.1996.492068

Cited by 38 publications

(14 citation statements)

References 16 publications

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“…To keep this contribution negligible, the oxide thickness of Flash cells has barely scaled with the technology generations, going from about 10 nm in the first prototype [3] to about 7-8 nm in the latest nodes [182]. However, experimental data [183][184][185][186][187][188] have demonstrated that, even if the SILC is reduced, there is a small number of cells that can exhibit a high leakage after stress, in analogy with the statistical behavior of RTN. An example of this effect is reported in Figure 16, where thin-oxide (6.5 nm) NOR Flash arrays were cycled heavily (10 4 P/E cycles) before being subjected to positive (left) or negative (right) oxide field to induce a V T shift [189]: note the distribution tails made up of cells featuring an enhanced leakage with respect to the main part of the distribution, whose shift is due to the intrinsic FN tunnelig current.…”

Section: Retention After Cycling and Silcmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Retention After Cycling and Silcmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…[1][2][3][4][5][6][7][8][9] In particular, anomalous SILC on local spots has been reported, which is some orders of magnitude larger than the average SILC, and it is a major factor in bit errors. [10][11][12][13][14][15] Therefore, it is important to reduce the probability of localized SILC generation in order to improve the reliability of flash memories. Many models for explaining SILC generation and flow mechanisms have been reported.…”

Section: Introductionmentioning

confidence: 99%

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Park

Teramoto

Kuroda

et al. 2018

Jpn. J. Appl. Phys.

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Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10 %17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure ) were experimentally determined for fabricated devices.

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“…SILC causes a severe limitation of the tunnel oxide scaling because a thinner oxide indicates a larger SILC [1]. Furthermore in flash memories anomalously larger leakage current that occurs at a localized spot, causes a severe bit error [2][3][4]. Such a phenomenon is often called anomalous SILC in flash memories.…”

Section: Introductionmentioning

confidence: 99%

Demonstrating distribution of SILC values at individual leakage spots

Inatsuka

Kuroda

Teramoto

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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Stress induced leakage current (SILC) in the order of 10 -17 to 10 -13 A were statistically evaluated by using an advanced test circuit. In this paper, the distribution of SILC was evaluated by changing measurement electric fields, electric stress intensities, device area, and oxide thickness. The distribution of SILC is determined by the current values at individual leakage spots when the device area is sufficiently small. When the electric stress intensity and the measurement field are small, the distribution of logarithm of SILC follows the Gumbel distribution because the maximum current values of the leakage spots determine the gate leakage current in small area MOSFETs. We also evaluated the time-dependent characteristics of SILC in small area MOSFETs. The random telegraph signals of gate leakage current were observed which also indicates the current values of individual leakage spots.

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Non-uniform current flow through thin oxide after Fowler-Nordheim current stress

Cited by 38 publications

References 16 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Demonstrating distribution of SILC values at individual leakage spots

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