Non-tree routing

Timing-Driven Interconnect Synthesis

“…Steiner points may also be introduced during this process to further optimize both delay and wirelength. Using a fast delay estimator to drive this process yields an efficient technique for synthesizing non-tree routing topologies with significantly improved performance characteristics (in terms of skew as well as delay), as compared with the corresponding initial trees [62,75]. Non-tree routing topologies can also be combined with wiresizing optimizations, as discussed above.…”

“…Thus, as VLSI interconnect becomes thinner and more resistive, non-tree routing topologies become increasingly attractive. McCoy and Robins [75] have studied the following Optimal Routing Graph (ORG) problem, which is a generalization of some of the routing problems discussed above.…”

“…The ORG problem is addressed algorithmically in [75] by starting with a reasonable initial topology (e.g., a heuristic Steiner or spanning tree), and greedily adding new edges to this topology so as to keep improving the specified delay objectives in the growing routing graph. Steiner points may also be introduced during this process to further optimize both delay and wirelength.…”

Minimum Steiner Tree Construction*

“…While recent routing formulations strive to achieve some of these objectives [5,12,27,45,50,52,57,67], much interesting research remains to be done in these areas.…”

“…In modern deep-submicron VLSI layout other criteria often dominate the routing objectives, such as path lengths, skew, density, inductance, manufacturability, electromigration, reliability, noise, power, non-Hanan topologies, signal integrity, three-dimensionality, alternate models, and various combinations and tradeoffs of these [3,5,12,27,44,45,46,50,52,57,67,70,86].…”