Non-Stationary Polar Codes for Resistive Memories

Zorgui, Marwen; Fouda, Mohammed E.; Wang, Zhiying; Eltawil, Ahmed M.; Kurdahi, Fadi

doi:10.1109/globecom38437.2019.9014026

Cited by 10 publications

(6 citation statements)

References 18 publications

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“…Channels with non-uniformity can be considered as channels with SNR variation [15] or non-stationary channels [9], [16]. These models have been studied in the ECC literature in the context of e.g., LDPC codes and Polar codes for storage applications [9], [15], [16]. However, these complex codes with long block length and high decoding latency (on the order µs [17]) are not compatible with the small decoding granularity and fast decoding requirements of the SCM applications.…”

Section: Channel Coding For Storage-class Memory (Scm) Applicationsmentioning

confidence: 99%

“…In an array with largely non-uniform device reliability, efficient ECC solutions must take this non-uniformity into consideration by either mitigating it or leveraging it. Channels with non-uniformity can be considered as channels with SNR variation [15] or non-stationary channels [9], [16]. These models have been studied in the ECC literature in the context of e.g., LDPC codes and Polar codes for storage applications [9], [15], [16].…”

Section: Channel Coding For Storage-class Memory (Scm) Applicationsmentioning

confidence: 99%

“…Designing error correction codes (ECCs) for the worst-case often leads to overly conservative code design and is therefore not rate efficient. For example, in [9], the authors designed a non-stationary polar code targeting channels with different reliability levels, which are characterized empirically by simulations. Moreover, [9] also showed that using more precise channel modeling, i.e., using the binary asymmetric channel (BAC) instead of the binary symmetric channel (BSC), provides an order of magnitude improvement in BER, which proves the necessity of precise channel models.…”

Section: Introductionmentioning

confidence: 99%

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Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

Chen

Dolecek

2020

GLOBECOM 2020 - 2020 IEEE Global Communications Conference

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Crossbar resistive memory with the 1 Selector 1 Resistor (1S1R) structure is attractive for nonvolatile, high-density, and low-latency storage-class memory applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. This paper presents write/read communication channels while considering the line resistance and device variabilities by statistically relating the degraded write/read margins and the channel parameters. Binary asymmetric channel (BAC) models are proposed for the write/read operations.Simulations based on these models suggest that the bit-error rate of devices are highly non-uniform across the memory array. These models provide quantitative tools for evaluating the trade-offs between memory reliability and design parameters, such as array size, technology nodes, and aspect ratio, and also for designing coding-theoretic solutions that would be most effective for crossbar memory. Method for optimizing the read threshold is proposed to reduce the raw bit-error rate (RBER). We propose two schemes for efficient channel coding based on Bose-Chaudhuri-Hocquenghem (BCH) codes. An interleaved coding scheme is proposed to mitigate the non-uniformity of reliability and a location dependent coding framework is proposed to leverage this non-uniformity. Both of our proposed coding schemes effectively reduce the undetected bit-error rate (UBER).

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Section: Channel Coding For Storage-class Memory (Scm) Applicationsmentioning

confidence: 99%

Section: Channel Coding For Storage-class Memory (Scm) Applicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

Chen

Dolecek

2020

GLOBECOM 2020 - 2020 IEEE Global Communications Conference

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“…For example, in [9], the authors proposed to use ECCs targeting the typical BER instead of the worst-case BER to improve system performance. In [10], the authors designed a non-stationary polar code targeting channels with different reliability levels, which are characterized empirically by simulations. Moreover, [10] also showed that using more precise channel modeling, i.e., using the binary asymmetric channel (BAC) instead of the binary symmetric channel (BSC), provides an order of magnitude improvement in BER, which proves the necessity of precise channel models.…”

Section: Introductionmentioning

confidence: 99%

Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

Chen

Dolecek

2019

Preprint

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Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is attractive for low-cost and high-density nonvolatile memory applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. This paper presents write/read communication channels while considering the line resistance and device variabilities by statistically relating the degraded write/read margins and the channel parameters. Binary asymmetric channel (BAC) models are proposed for the write/read operations and array capacity results are presented. Simulations based on these models suggest that the bit-error rate of devices are highly non-uniform across the memory array. These models provide quantitative tools for evaluating the trade-offs between memory reliability and design parameters, such as array size, technology nodes, and aspect ratio, and also for designing codingtheoretic solutions that would be most effective for crossbar memory.

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“…However, so far limited work has been done on error correction coding for ReRAM. In particular, a non-stationary polar coding scheme for ReRAM was proposed by [17], which is mainly aimed to address the raw bit error rate (BER) diversity among different bitlines, rather than tacking the sneak path interference. In [16], an across-array coding strategy is proposed, which assigns a codeword to multiple memory arrays.…”

mentioning

confidence: 99%

Belief Propagation based Joint Detection and Decoding for Resistive Random Access Memories

Sun¹,

Cai²,

Song³

et al. 2021

Preprint

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Despite the great promises that the resistive random access memory (ReRAM) has shown as the next generation of non-volatile memory technology, its crossbar array structure leads to a severe sneak path interference to the signal read back from the memory cell. In this paper, we first propose a novel belief propagation (BP) based detector for the sneak path interference in ReRAM. Based on the conditions for a sneak path to occur and the dependence of the states of the memory cells that are involved in the sneak path, a Tanner graph for the ReRAM channel is constructed, inside which specific messages are updated iteratively to get a better estimation of the sneak path affected cells. We further combine the graph of the designed BP detector with that of the BP decoder of the polar codes to form a joint detector and decoder. Tailored for the joint detector and decoder over the ReRAM channel, effective polar codes are constructed using the genetic algorithm. Simulation results show that the BP detector Ce Sun, Zesong Fei are with the

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Non-Stationary Polar Codes for Resistive Memories

Cited by 10 publications

References 18 publications

Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

Write and Read Channel Models for 1S1R Crossbar Resistive Memory with High Line Resistance

Belief Propagation based Joint Detection and Decoding for Resistive Random Access Memories

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